Date: Mon, 08 May 2000 15:08:27 -0400 From: James Housley <jim@thehousleys.net> To: Matthew Dillon <dillon@apollo.backplane.com> Cc: Terry Lambert <tlambert@primenet.com>, Jeremiah Gowdy <jgowdy@home.com>, Steve Passe <smp@csn.net>, freebsd-smp@FreeBSD.ORG Subject: Re: hlt instructions and temperature issues Message-ID: <391710AB.B6C680AC@thehousleys.net> References: <200004282108.OAA01313@usr08.primenet.com> <200004282240.PAA14200@apollo.backplane.com>
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Matthew Dillon wrote:
> I like the HLT + IPI idea, but none of the patches to date really cover
> the bases and switching performance is not going to be as good as when you
> don't have the HLT due to the overhead of sending the IPIs and having to
> keep track of which cpu's are in a HLT'd state and which are not (so you
> don't send IPI's to all cpu's gratuitously).
>
> This is not a trivial problem because we cannot afford to have N cpu's
> all trying to do locked bitset instructions on the same memory location
> in order to go idle -- that alone will create big latencies.
Just a thought after reading this thread. Might it make sense to
implement a simple form of this or a similar scheme for the
dual-processor system? There would only be 1 processor accessing the
lock-memory location. Dual processor systems are leaving the server
only areana and entering user/power-user areana.
Then work on a more elegant solution the 4-way and above, I know i
skipped the 3-way.
Jim
--
"...there's no idea that's so good you can't
ruin it with a few well-placed idiots."
-- Charles Spickman
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