From owner-cvs-sys Mon Oct 7 16:23:19 1996 Return-Path: owner-cvs-sys Received: (from root@localhost) by freefall.freebsd.org (8.7.5/8.7.3) id QAA08195 for cvs-sys-outgoing; Mon, 7 Oct 1996 16:23:19 -0700 (PDT) Received: from veda.is (root@ubiq.veda.is [193.4.230.60]) by freefall.freebsd.org (8.7.5/8.7.3) with ESMTP id QAA08179; Mon, 7 Oct 1996 16:23:06 -0700 (PDT) Received: (from adam@localhost) by veda.is (8.7.6/8.7.3) id XAA06650; Mon, 7 Oct 1996 23:22:12 GMT From: Adam David Message-Id: <199610072322.XAA06650@veda.is> Subject: Re: cvs commit: src/sys/vm vm_page.h To: dyson@freebsd.org Date: Mon, 7 Oct 1996 23:22:11 +0000 (GMT) Cc: guido@gvr.win.tue.nl, dyson@freebsd.org, dyson@freefall.freebsd.org, CVS-committers@freefall.freebsd.org, cvs-all@freefall.freebsd.org, cvs-sys@freefall.freebsd.org In-Reply-To: <199610072234.RAA03072@dyson.iquest.net> from "John S. Dyson" at "Oct 7, 96 05:34:26 pm" X-Mailer: ELM [version 2.4ME+ PL22 (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: owner-cvs-sys@freebsd.org X-Loop: FreeBSD.org Precedence: bulk > > > > Perhaps we could introduce a new word in the kernel config file. > > > > Something like > > > > cache > > > > where is the amount of L2 cache. The L1 cache is processor specific > > > > and thus can be obtained via the cpu directive. The rest can then be > > > > doen with macros. > > > > > > > Actually, the L1 cache will be changing on P5 class machines soon. > > > > hmm. But that would be identifiable by the stepping number, right? > In the longer term (probably in release timeframe) an attempt to probe > the system interface chips would be useful, upon failure, perhaps > default to 256K. (Most reasonably high perf systems since the > 386 and certainly the 486 have 256K (maybe some 128K) cache.) It > is only the medium 386s that had 64K anyway. ... and Cx486-DLC Also some systems might be supplied without L2 cache altogether, or the cache misconfigured so it is equivalent to non-existence. Is there no reliable probe for cache size that could be coaxed to work on all systems? == Adam