From owner-freebsd-arm@FreeBSD.ORG Sat May 10 18:52:27 2014 Return-Path: Delivered-To: freebsd-arm@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 19FEACC4; Sat, 10 May 2014 18:52:27 +0000 (UTC) Received: from mho-02-ewr.mailhop.org (mho-02-ewr.mailhop.org [204.13.248.72]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id E1B2CDF2; Sat, 10 May 2014 18:52:26 +0000 (UTC) Received: from c-24-8-230-52.hsd1.co.comcast.net ([24.8.230.52] helo=damnhippie.dyndns.org) by mho-02-ewr.mailhop.org with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.72) (envelope-from ) id 1WjCNl-0007ge-4M; Sat, 10 May 2014 18:52:25 +0000 Received: from [172.22.42.240] (revolution.hippie.lan [172.22.42.240]) by damnhippie.dyndns.org (8.14.3/8.14.3) with ESMTP id s4AIqN1S031978; Sat, 10 May 2014 12:52:23 -0600 (MDT) (envelope-from ian@FreeBSD.org) X-Mail-Handler: Dyn Standard SMTP by Dyn X-Originating-IP: 24.8.230.52 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/sendlabs/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX187V/oj+ZRcT5IRGHNGKwWY Subject: Re: Fast cycle counter for ARM chips with SCC - patch for review. From: Ian Lepore To: Mark R V Murray In-Reply-To: <22E12094-E6B2-42F9-94AB-014A702D17F2@FreeBSD.org> References: <22E12094-E6B2-42F9-94AB-014A702D17F2@FreeBSD.org> Content-Type: text/plain; charset="iso-8859-7" Date: Sat, 10 May 2014 12:52:23 -0600 Message-ID: <1399747943.22079.415.camel@revolution.hippie.lan> Mime-Version: 1.0 X-Mailer: Evolution 2.32.1 FreeBSD GNOME Team Port Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by damnhippie.dyndns.org id s4AIqN1S031978 Cc: freebsd-arm X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 10 May 2014 18:52:27 -0000 On Sat, 2014-05-10 at 18:39 +0100, Mark R V Murray wrote: > Hi * >=20 > This patch makes the ARM6 kernels that have an SCC coprocessor (RPI and= WANDBOARD have them) get a MUCH better implementation of get_cyclecount(= 9), but not a perfect one. The incrementing rate is good (+- 1 per instru= ction), but its only 32 bits. Later, if there is interest, I may wish to = fix that with an overflow interrupt, but for now its easily good enough f= or the kernel entropy harvesting service. Also, its MUUUCH more efficient= ; a simple read rather can calling the internal kernel binuptime(9) clock. >=20 > Comments, please? I=A2m keen to commit. >=20 > M The manual says setting the user enable bit doesn't just enable user read, it also grants user write access to most of the registers, including CCNT. The value to write to PMINTENCLR should be 0xffffffff. In theory you should read the ID register to see how many counters are available and set that many of the low-order bits to 1, but the manual says that writes are ignored for the bits 30-N so you can just blindly write all ones. For PMCNTENSET I think the value to write is 0x80000000, no need to enable other counters. The comment says PMCR is set to 1, but it's actually set to 7. The comment=20 This '#if' asks the question 'Do we have a System Control Coprocessor? should read something like 'Does CP15 include performance counters?' all arm chips have a system control coprocessor. -- Ian