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From: Adrian Chadd <adrian@FreeBSD.org>
Date: Sun, 16 Mar 2014 08:38:31 +0000 (UTC)
To: src-committers@freebsd.org, svn-src-all@freebsd.org,
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Subject: svn commit: r263228 - head/sys/mips/atheros
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Author: adrian
Date: Sun Mar 16 08:38:31 2014
New Revision: 263228
URL: http://svnweb.freebsd.org/changeset/base/263228

Log:
  * Handle the three other timer interrupts for now, from the AR724x
    later.  If the interrupts are ACKed even if they're not masked, we get
    the interrupts again later.  Grr.
  
  * The AR724x and later chips want the interrupt bits cleared by writing the
    relevant bit to it, NOT by writing all but the current interrupt to it.
  
  Tested:
  
  * AR9344, DB120 reference board
  
  TODO:
  
  * Test ar724x and later chips to ensure no regressions have occured.

Modified:
  head/sys/mips/atheros/apb.c

Modified: head/sys/mips/atheros/apb.c
==============================================================================
--- head/sys/mips/atheros/apb.c	Sun Mar 16 08:04:06 2014	(r263227)
+++ head/sys/mips/atheros/apb.c	Sun Mar 16 08:38:31 2014	(r263228)
@@ -362,9 +362,9 @@ apb_filter(void *arg)
 			case AR71XX_SOC_AR9341:
 			case AR71XX_SOC_AR9342:
 			case AR71XX_SOC_AR9344:
-				/* Ack/clear the irq on status register for AR724x */
+				/* ACK/clear the given interrupt */
 				ATH_WRITE_REG(AR71XX_MISC_INTR_STATUS,
-				    reg & ~(1 << irq));
+				    (1 << irq));
 				break;
 			default:
 				/* fallthrough */
@@ -385,7 +385,7 @@ apb_filter(void *arg)
 					continue;
 				}
 				/* Ignore timer interrupts */
-				if (irq != 0)
+				if (irq != 0 && irq != 8 && irq != 9 && irq != 10)
 					printf("Stray APB IRQ %d\n", irq);
 				continue;
 			}