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From: Adrian Chadd <adrian@FreeBSD.org>
Date: Sun, 16 Mar 2014 08:39:46 +0000 (UTC)
To: src-committers@freebsd.org, svn-src-all@freebsd.org,
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Subject: svn commit: r263229 - head/sys/mips/atheros
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Author: adrian
Date: Sun Mar 16 08:39:46 2014
New Revision: 263229
URL: http://svnweb.freebsd.org/changeset/base/263229

Log:
  The AR71xx has APB interrupts in the MISC registers from 0-7, later
  chips have more.
  
  So for now, let's allow more.  We should teach the apb code to just
  reject interrupts that lie outside what the chip can do at runtime.

Modified:
  head/sys/mips/atheros/apbvar.h

Modified: head/sys/mips/atheros/apbvar.h
==============================================================================
--- head/sys/mips/atheros/apbvar.h	Sun Mar 16 08:38:31 2014	(r263228)
+++ head/sys/mips/atheros/apbvar.h	Sun Mar 16 08:39:46 2014	(r263229)
@@ -23,21 +23,23 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
+ * $FreeBSD$
  */
 
 #ifndef _APBVAR_H_
 #define _APBVAR_H_
 
 #define	APB_IRQ_BASE		0
-#define	APB_IRQ_END		7
-#define	APB_NIRQS		8
+#define	APB_IRQ_END		31
+#define	APB_NIRQS		32
 
 struct apb_softc {
 	struct rman		apb_irq_rman;
 	struct rman		apb_mem_rman;
 	/* IRQ events structs for child devices */
-	struct intr_event	*sc_eventstab[APB_NIRQS];	
-	mips_intrcnt_t		sc_intr_counter[APB_NIRQS];	
+	struct intr_event	*sc_eventstab[APB_NIRQS];
+	mips_intrcnt_t		sc_intr_counter[APB_NIRQS];
 	/* Resources and cookies for MIPS CPU INTs */
 	struct resource		*sc_misc_irq;
 	void			*sc_misc_ih;