From owner-svn-src-stable@FreeBSD.ORG Sat Sep 13 16:02:44 2014 Return-Path: Delivered-To: svn-src-stable@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 009A341F; Sat, 13 Sep 2014 16:02:43 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id D47AB954; Sat, 13 Sep 2014 16:02:43 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id s8DG2hjF098699; Sat, 13 Sep 2014 16:02:43 GMT (envelope-from mav@FreeBSD.org) Received: (from mav@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id s8DG2hXE098698; Sat, 13 Sep 2014 16:02:43 GMT (envelope-from mav@FreeBSD.org) Message-Id: <201409131602.s8DG2hXE098698@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: mav set sender to mav@FreeBSD.org using -f From: Alexander Motin Date: Sat, 13 Sep 2014 16:02:43 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r271523 - stable/10/sys/dev/ahci X-SVN-Group: stable-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 13 Sep 2014 16:02:44 -0000 Author: mav Date: Sat Sep 13 16:02:43 2014 New Revision: 271523 URL: http://svnweb.freebsd.org/changeset/base/271523 Log: MFC r271163, 271196: Invert AHCI_Q_NOBSYRES quirk meaning, waiting for readiness by default. I gave up to update list of Marvell chips that require this quirk. The final nail was growing number of PCIe/M.2 SSDs where Marvell chips have PCI IDs of different vendors. Approved by: re (delphij) Modified: stable/10/sys/dev/ahci/ahci.c Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/dev/ahci/ahci.c ============================================================================== --- stable/10/sys/dev/ahci/ahci.c Sat Sep 13 16:00:35 2014 (r271522) +++ stable/10/sys/dev/ahci/ahci.c Sat Sep 13 16:02:43 2014 (r271523) @@ -257,31 +257,31 @@ static struct { AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH | AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, - {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES}, - {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, - {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES}, - {0x91251b4b, 0x00, "Marvell 88SE9125", AHCI_Q_NOBSYRES}, - {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, - {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, - {0x91721b4b, 0x00, "Marvell 88SE9172", AHCI_Q_NOBSYRES}, - {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES}, - {0x91831b4b, 0x00, "Marvell 88SS9183", AHCI_Q_NOBSYRES}, - {0x91a01b4b, 0x00, "Marvell 88SE91Ax", AHCI_Q_NOBSYRES}, - {0x92151b4b, 0x00, "Marvell 88SE9215", AHCI_Q_NOBSYRES}, - {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, - {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, - {0x92351b4b, 0x00, "Marvell 88SE9235", AHCI_Q_NOBSYRES}, - {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, - {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, - {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, - {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, - {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, - {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, - {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, - {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, - {0x06411103, 0x00, "HighPoint RocketRAID 640L", AHCI_Q_NOBSYRES}, - {0x06421103, 0x00, "HighPoint RocketRAID 642L", AHCI_Q_NOBSYRES}, - {0x06451103, 0x00, "HighPoint RocketRAID 644L", AHCI_Q_NOBSYRES}, + {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS}, + {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_ALTSIG}, + {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2}, + {0x91251b4b, 0x00, "Marvell 88SE9125", 0}, + {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_ALTSIG}, + {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_ALTSIG}, + {0x91721b4b, 0x00, "Marvell 88SE9172", 0}, + {0x91821b4b, 0x00, "Marvell 88SE9182", 0}, + {0x91831b4b, 0x00, "Marvell 88SS9183", 0}, + {0x91a01b4b, 0x00, "Marvell 88SE91Ax", 0}, + {0x92151b4b, 0x00, "Marvell 88SE9215", 0}, + {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_ALTSIG}, + {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_ALTSIG}, + {0x92351b4b, 0x00, "Marvell 88SE9235", 0}, + {0x06201103, 0x00, "HighPoint RocketRAID 620", 0}, + {0x06201b4b, 0x00, "HighPoint RocketRAID 620", 0}, + {0x06221103, 0x00, "HighPoint RocketRAID 622", 0}, + {0x06221b4b, 0x00, "HighPoint RocketRAID 622", 0}, + {0x06401103, 0x00, "HighPoint RocketRAID 640", 0}, + {0x06401b4b, 0x00, "HighPoint RocketRAID 640", 0}, + {0x06441103, 0x00, "HighPoint RocketRAID 644", 0}, + {0x06441b4b, 0x00, "HighPoint RocketRAID 644", 0}, + {0x06411103, 0x00, "HighPoint RocketRAID 640L", 0}, + {0x06421103, 0x00, "HighPoint RocketRAID 642L", 0}, + {0x06451103, 0x00, "HighPoint RocketRAID 644L", 0}, {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, @@ -491,10 +491,9 @@ ahci_attach(device_t dev) ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ - if ((ctlr->quirks & AHCI_Q_NOBSYRES) && - (ctlr->quirks & AHCI_Q_ALTSIG) && + if ((ctlr->quirks & AHCI_Q_ALTSIG) && (ctlr->caps & AHCI_CAP_SPM) == 0) - ctlr->quirks &= ~AHCI_Q_NOBSYRES; + ctlr->quirks |= AHCI_Q_NOBSYRES; if (ctlr->quirks & AHCI_Q_1CH) { ctlr->caps &= ~AHCI_CAP_NPMASK; @@ -1988,9 +1987,15 @@ ahci_execute_transaction(struct ahci_slo } } - /* Marvell controllers do not wait for readyness. */ - if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 && - et == AHCI_ERR_NONE) { + /* + * Marvell HBAs with non-RAID firmware do not wait for + * readiness after soft reset, so we have to wait here. + * Marvell RAIDs do not have this problem, but instead + * sometimes forget to update FIS receive area, breaking + * this wait. + */ + if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 && + softreset == 2 && et == AHCI_ERR_NONE) { while ((val = fis[2]) & ATA_S_BUSY) { DELAY(10); if (count++ >= timeout)