From owner-svn-src-stable@FreeBSD.ORG Thu Jun 21 10:41:28 2012 Return-Path: Delivered-To: svn-src-stable@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 064AA106566B; Thu, 21 Jun 2012 10:41:28 +0000 (UTC) (envelope-from mav@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id E42438FC08; Thu, 21 Jun 2012 10:41:27 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id q5LAfRdr007480; Thu, 21 Jun 2012 10:41:27 GMT (envelope-from mav@svn.freebsd.org) Received: (from mav@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id q5LAfRwH007476; Thu, 21 Jun 2012 10:41:27 GMT (envelope-from mav@svn.freebsd.org) Message-Id: <201206211041.q5LAfRwH007476@svn.freebsd.org> From: Alexander Motin Date: Thu, 21 Jun 2012 10:41:27 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org X-SVN-Group: stable-8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r237379 - stable/8/sys/dev/mvs X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jun 2012 10:41:28 -0000 Author: mav Date: Thu Jun 21 10:41:27 2012 New Revision: 237379 URL: http://svn.freebsd.org/changeset/base/237379 Log: MFC r236952: - Limit r214102 workaround to only x86. On arm it causes more problems then solves because of cache coherency issues. This fixes periodic error messages on console and command timeouts. - Patch SATA PHY configuration for 65nm SoCs to improve SNR same as Linux does. Modified: stable/8/sys/dev/mvs/mvs.c stable/8/sys/dev/mvs/mvs.h stable/8/sys/dev/mvs/mvs_soc.c Directory Properties: stable/8/sys/ (props changed) Modified: stable/8/sys/dev/mvs/mvs.c ============================================================================== --- stable/8/sys/dev/mvs/mvs.c Thu Jun 21 10:28:59 2012 (r237378) +++ stable/8/sys/dev/mvs/mvs.c Thu Jun 21 10:41:27 2012 (r237379) @@ -1047,14 +1047,19 @@ mvs_crbq_intr(device_t dev) * Handle only successfull completions here. * Errors will be handled by main intr handler. */ +#if defined(__i386__) || defined(__amd64__) if (crpb->id == 0xffff && crpb->rspflg == 0xffff) { device_printf(dev, "Unfilled CRPB " "%d (%d->%d) tag %d flags %04x rs %08x\n", cin_idx, fin_idx, in_idx, slot, flags, ch->rslots); - } else if (ch->numtslots != 0 || + } else +#endif + if (ch->numtslots != 0 || (flags & EDMA_IE_EDEVERR) == 0) { +#if defined(__i386__) || defined(__amd64__) crpb->id = 0xffff; crpb->rspflg = 0xffff; +#endif if (ch->slot[slot].state >= MVS_SLOT_RUNNING) { ccb = ch->slot[slot].ccb; ccb->ataio.res.status = @@ -1998,6 +2003,39 @@ mvs_reset_to(void *arg) } static void +mvs_errata(device_t dev) +{ + struct mvs_channel *ch = device_get_softc(dev); + uint32_t val; + + if (ch->quirks & MVS_Q_SOC65) { + val = ATA_INL(ch->r_mem, SATA_PHYM3); + val &= ~(0x3 << 27); /* SELMUPF = 1 */ + val |= (0x1 << 27); + val &= ~(0x3 << 29); /* SELMUPI = 1 */ + val |= (0x1 << 29); + ATA_OUTL(ch->r_mem, SATA_PHYM3, val); + + val = ATA_INL(ch->r_mem, SATA_PHYM4); + val &= ~0x1; /* SATU_OD8 = 0 */ + val |= (0x1 << 16); /* reserved bit 16 = 1 */ + ATA_OUTL(ch->r_mem, SATA_PHYM4, val); + + val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN2); + val &= ~0xf; /* TXAMP[3:0] = 8 */ + val |= 0x8; + val &= ~(0x1 << 14); /* TXAMP[4] = 0 */ + ATA_OUTL(ch->r_mem, SATA_PHYM9_GEN2, val); + + val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN1); + val &= ~0xf; /* TXAMP[3:0] = 8 */ + val |= 0x8; + val &= ~(0x1 << 14); /* TXAMP[4] = 0 */ + ATA_OUTL(ch->r_mem, SATA_PHYM9_GEN1, val); + } +} + +static void mvs_reset(device_t dev) { struct mvs_channel *ch = device_get_softc(dev); @@ -2043,6 +2081,7 @@ mvs_reset(device_t dev) ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EATARST); DELAY(25); ATA_OUTL(ch->r_mem, EDMA_CMD, 0); + mvs_errata(dev); /* Reset and reconnect PHY, */ if (!mvs_sata_phy_reset(dev)) { if (bootverbose) Modified: stable/8/sys/dev/mvs/mvs.h ============================================================================== --- stable/8/sys/dev/mvs/mvs.h Thu Jun 21 10:28:59 2012 (r237378) +++ stable/8/sys/dev/mvs/mvs.h Thu Jun 21 10:41:27 2012 (r237379) @@ -379,6 +379,10 @@ #define SATA_FISDW5 0x384 /* FIS DW5 */ #define SATA_FISDW6 0x388 /* FIS DW6 */ +#define SATA_PHYM9_GEN2 0x398 +#define SATA_PHYM9_GEN1 0x39c +#define SATA_PHYCFG_OFS 0x3a0 /* 65nm SoCs only */ + #define MVS_MAX_PORTS 8 #define MVS_MAX_SLOTS 32 @@ -534,6 +538,7 @@ struct mvs_channel { #define MVS_Q_GENIIE 4 #define MVS_Q_SOC 8 #define MVS_Q_CT 16 +#define MVS_Q_SOC65 32 int pm_level; /* power management level */ struct mvs_slot slot[MVS_MAX_SLOTS]; Modified: stable/8/sys/dev/mvs/mvs_soc.c ============================================================================== --- stable/8/sys/dev/mvs/mvs_soc.c Thu Jun 21 10:28:59 2012 (r237378) +++ stable/8/sys/dev/mvs/mvs_soc.c Thu Jun 21 10:41:27 2012 (r237379) @@ -130,6 +130,8 @@ mvs_attach(device_t dev) if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &ctlr->r_rid, RF_ACTIVE))) return ENXIO; + if (ATA_INL(ctlr->r_mem, PORT_BASE(0) + SATA_PHYCFG_OFS) != 0) + ctlr->quirks |= MVS_Q_SOC65; /* Setup our own memory management for channels. */ ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);