From owner-svn-src-all@freebsd.org Mon Aug 26 16:12:15 2019 Return-Path: Delivered-To: svn-src-all@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 7F52BDF271; Mon, 26 Aug 2019 16:12:15 +0000 (UTC) (envelope-from tuexen@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 46HH8H2nMsz4bVZ; Mon, 26 Aug 2019 16:12:15 +0000 (UTC) (envelope-from tuexen@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 42BFA89F1; Mon, 26 Aug 2019 16:12:15 +0000 (UTC) (envelope-from tuexen@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x7QGCFDk079251; Mon, 26 Aug 2019 16:12:15 GMT (envelope-from tuexen@FreeBSD.org) Received: (from tuexen@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x7QGCEOR079250; Mon, 26 Aug 2019 16:12:14 GMT (envelope-from tuexen@FreeBSD.org) Message-Id: <201908261612.x7QGCEOR079250@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: tuexen set sender to tuexen@FreeBSD.org using -f From: Michael Tuexen Date: Mon, 26 Aug 2019 16:12:14 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r351511 - in head/sys/arm64: arm64 include X-SVN-Group: head X-SVN-Commit-Author: tuexen X-SVN-Commit-Paths: in head/sys/arm64: arm64 include X-SVN-Commit-Revision: 351511 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 26 Aug 2019 16:12:15 -0000 Author: tuexen Date: Mon Aug 26 16:12:14 2019 New Revision: 351511 URL: https://svnweb.freebsd.org/changeset/base/351511 Log: Identify eMAG CPU used in Ampere Computing systems. Reviewed by: emaste@ MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D21314 Modified: head/sys/arm64/arm64/identcpu.c head/sys/arm64/include/cpu.h Modified: head/sys/arm64/arm64/identcpu.c ============================================================================== --- head/sys/arm64/arm64/identcpu.c Mon Aug 26 15:21:29 2019 (r351510) +++ head/sys/arm64/arm64/identcpu.c Mon Aug 26 16:12:14 2019 (r351511) @@ -168,6 +168,12 @@ static const struct cpu_parts cpu_parts_cavium[] = { CPU_PART_NONE, }; +/* APM / Ampere */ +static const struct cpu_parts cpu_parts_apm[] = { + { CPU_PART_EMAG8180, "eMAG 8180" }, + CPU_PART_NONE, +}; + /* Unknown */ static const struct cpu_parts cpu_parts_none[] = { CPU_PART_NONE, @@ -184,7 +190,7 @@ const struct cpu_implementers cpu_implementers[] = { { CPU_IMPL_INFINEON, "IFX", cpu_parts_none }, { CPU_IMPL_FREESCALE, "Freescale", cpu_parts_none }, { CPU_IMPL_NVIDIA, "NVIDIA", cpu_parts_none }, - { CPU_IMPL_APM, "APM", cpu_parts_none }, + { CPU_IMPL_APM, "APM", cpu_parts_apm }, { CPU_IMPL_QUALCOMM, "Qualcomm", cpu_parts_none }, { CPU_IMPL_MARVELL, "Marvell", cpu_parts_none }, { CPU_IMPL_INTEL, "Intel", cpu_parts_none }, Modified: head/sys/arm64/include/cpu.h ============================================================================== --- head/sys/arm64/include/cpu.h Mon Aug 26 15:21:29 2019 (r351510) +++ head/sys/arm64/include/cpu.h Mon Aug 26 16:12:14 2019 (r351511) @@ -100,6 +100,9 @@ #define CPU_REV_THUNDERX2_0 0x00 +/* APM / Ampere Part Number */ +#define CPU_PART_EMAG8180 0x000 + #define CPU_IMPL(midr) (((midr) >> 24) & 0xff) #define CPU_PART(midr) (((midr) >> 4) & 0xfff) #define CPU_VAR(midr) (((midr) >> 20) & 0xf)