From owner-svn-src-head@FreeBSD.ORG Tue Jun 5 14:20:00 2012 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 5FF27106566C; Tue, 5 Jun 2012 14:20:00 +0000 (UTC) (envelope-from imp@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 49FD38FC08; Tue, 5 Jun 2012 14:20:00 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id q55EK0H3024583; Tue, 5 Jun 2012 14:20:00 GMT (envelope-from imp@svn.freebsd.org) Received: (from imp@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id q55EK0Sl024580; Tue, 5 Jun 2012 14:20:00 GMT (envelope-from imp@svn.freebsd.org) Message-Id: <201206051420.q55EK0Sl024580@svn.freebsd.org> From: Warner Losh Date: Tue, 5 Jun 2012 14:20:00 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r236617 - head/sys/arm/at91 X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Jun 2012 14:20:00 -0000 Author: imp Date: Tue Jun 5 14:19:59 2012 New Revision: 236617 URL: http://svn.freebsd.org/changeset/base/236617 Log: Remove dead code. Modified: head/sys/arm/at91/at91rm92reg.h Modified: head/sys/arm/at91/at91rm92reg.h ============================================================================== --- head/sys/arm/at91/at91rm92reg.h Tue Jun 5 13:57:02 2012 (r236616) +++ head/sys/arm/at91/at91rm92reg.h Tue Jun 5 14:19:59 2012 (r236617) @@ -91,146 +91,6 @@ #define AT91RM92_SYS_BASE 0xffff000 #define AT91RM92_SYS_SIZE 0x1000 -#if 0 -/* Interrupt Controller */ -#define IC_SMR (0) /* Source mode register */ -#define IC_SVR (128) /* Source vector register */ -#define IC_IVR (256) /* IRQ vector register */ -#define IC_FVR (260) /* FIQ vector register */ -#define IC_ISR (264) /* Interrupt status register */ -#define IC_IPR (268) /* Interrupt pending register */ -#define IC_IMR (272) /* Interrupt status register */ -#define IC_CISR (276) /* Core interrupt status register */ -#define IC_IECR (288) /* Interrupt enable command register */ -#define IC_IDCR (292) /* Interrupt disable command register */ -#define IC_ICCR (296) /* Interrupt clear command register */ -#define IC_ISCR (300) /* Interrupt set command register */ -#define IC_EOICR (304) /* End of interrupt command register */ -#define IC_SPU (308) /* Spurious vector register */ -#define IC_DCR (312) /* Debug control register */ -#define IC_FFER (320) /* Fast forcing enable register */ -#define IC_FFDR (324) /* Fast forcing disable register */ -#define IC_FFSR (328) /* Fast forcing status register */ - - -#define PIOA_PER (0x400) /* PIO Enable Register */ -#define PIOA_PDR (0x400 + 4) /* PIO Disable Register */ -#define PIOA_PSR (0x400 + 8) /* PIO status register */ -#define PIOA_OER (0x400 + 16) /* Output enable register */ -#define PIOA_ODR (0x400 + 20) /* Output disable register */ -#define PIOA_OSR (0x400 + 24) /* Output status register */ -#define PIOA_IFER (0x400 + 32) /* Input filter enable register */ -#define PIOA_IFDR (0x400 + 36) /* Input filter disable register */ -#define PIOA_IFSR (0x400 + 40) /* Input filter status register */ -#define PIOA_SODR (0x400 + 48) /* Set output data register */ -#define PIOA_CODR (0x400 + 52) /* Clear output data register */ -#define PIOA_ODSR (0x400 + 56) /* Output data status register */ -#define PIOA_PDSR (0x400 + 60) /* Pin data status register */ -#define PIOA_IER (0x400 + 64) /* Interrupt enable register */ -#define PIOA_IDR (0x400 + 68) /* Interrupt disable register */ -#define PIOA_IMR (0x400 + 72) /* Interrupt mask register */ -#define PIOA_ISR (0x400 + 76) /* Interrupt status register */ -#define PIOA_MDER (0x400 + 80) /* Multi driver enable register */ -#define PIOA_MDDR (0x400 + 84) /* Multi driver disable register */ -#define PIOA_MDSR (0x400 + 88) /* Multi driver status register */ -#define PIOA_PPUDR (0x400 + 96) /* Pull-up disable register */ -#define PIOA_PPUER (0x400 + 100) /* Pull-up enable register */ -#define PIOA_PPUSR (0x400 + 104) /* Pad pull-up status register */ -#define PIOA_ASR (0x400 + 112) /* Select A register */ -#define PIOA_BSR (0x400 + 116) /* Select B register */ -#define PIOA_ABSR (0x400 + 120) /* AB Select status register */ -#define PIOA_OWER (0x400 + 160) /* Output Write enable register */ -#define PIOA_OWDR (0x400 + 164) /* Output write disable register */ -#define PIOA_OWSR (0x400 + 168) /* Output write status register */ -#define PIOB_PER (0x400) /* PIO Enable Register */ -#define PIOB_PDR (0x600 + 4) /* PIO Disable Register */ -#define PIOB_PSR (0x600 + 8) /* PIO status register */ -#define PIOB_OER (0x600 + 16) /* Output enable register */ -#define PIOB_ODR (0x600 + 20) /* Output disable register */ -#define PIOB_OSR (0x600 + 24) /* Output status register */ -#define PIOB_IFER (0x600 + 32) /* Input filter enable register */ -#define PIOB_IFDR (0x600 + 36) /* Input filter disable register */ -#define PIOB_IFSR (0x600 + 40) /* Input filter status register */ -#define PIOB_SODR (0x600 + 48) /* Set output data register */ -#define PIOB_CODR (0x600 + 52) /* Clear output data register */ -#define PIOB_ODSR (0x600 + 56) /* Output data status register */ -#define PIOB_PDSR (0x600 + 60) /* Pin data status register */ -#define PIOB_IER (0x600 + 64) /* Interrupt enable register */ -#define PIOB_IDR (0x600 + 68) /* Interrupt disable register */ -#define PIOB_IMR (0x600 + 72) /* Interrupt mask register */ -#define PIOB_ISR (0x600 + 76) /* Interrupt status register */ -#define PIOB_MDER (0x600 + 80) /* Multi driver enable register */ -#define PIOB_MDDR (0x600 + 84) /* Multi driver disable register */ -#define PIOB_MDSR (0x600 + 88) /* Multi driver status register */ -#define PIOB_PPUDR (0x600 + 96) /* Pull-up disable register */ -#define PIOB_PPUER (0x600 + 100) /* Pull-up enable register */ -#define PIOB_PPUSR (0x600 + 104) /* Pad pull-up status register */ -#define PIOB_ASR (0x600 + 112) /* Select A register */ -#define PIOB_BSR (0x600 + 116) /* Select B register */ -#define PIOB_ABSR (0x600 + 120) /* AB Select status register */ -#define PIOB_OWER (0x600 + 160) /* Output Write enable register */ -#define PIOB_OWDR (0x600 + 164) /* Output write disable register */ -#define PIOB_OWSR (0x600 + 168) /* Output write status register */ -#define PIOC_PER (0x800) /* PIO Enable Register */ -#define PIOC_PDR (0x800 + 4) /* PIO Disable Register */ -#define PIOC_PSR (0x800 + 8) /* PIO status register */ -#define PIOC_OER (0x800 + 16) /* Output enable register */ -#define PIOC_ODR (0x800 + 20) /* Output disable register */ -#define PIOC_OSR (0x800 + 24) /* Output status register */ -#define PIOC_IFER (0x800 + 32) /* Input filter enable register */ -#define PIOC_IFDR (0x800 + 36) /* Input filter disable register */ -#define PIOC_IFSR (0x800 + 40) /* Input filter status register */ -#define PIOC_SODR (0x800 + 48) /* Set output data register */ -#define PIOC_CODR (0x800 + 52) /* Clear output data register */ -#define PIOC_ODSR (0x800 + 56) /* Output data status register */ -#define PIOC_PDSR (0x800 + 60) /* Pin data status register */ -#define PIOC_IER (0x800 + 64) /* Interrupt enable register */ -#define PIOC_IDR (0x800 + 68) /* Interrupt disable register */ -#define PIOC_IMR (0x800 + 72) /* Interrupt mask register */ -#define PIOC_ISR (0x800 + 76) /* Interrupt status register */ -#define PIOC_MDER (0x800 + 80) /* Multi driver enable register */ -#define PIOC_MDDR (0x800 + 84) /* Multi driver disable register */ -#define PIOC_MDSR (0x800 + 88) /* Multi driver status register */ -#define PIOC_PPUDR (0x800 + 96) /* Pull-up disable register */ -#define PIOC_PPUER (0x800 + 100) /* Pull-up enable register */ -#define PIOC_PPUSR (0x800 + 104) /* Pad pull-up status register */ -#define PIOC_ASR (0x800 + 112) /* Select A register */ -#define PIOC_BSR (0x800 + 116) /* Select B register */ -#define PIOC_ABSR (0x800 + 120) /* AB Select status register */ -#define PIOC_OWER (0x800 + 160) /* Output Write enable register */ -#define PIOC_OWDR (0x800 + 164) /* Output write disable register */ -#define PIOC_OWSR (0x800 + 168) /* Output write status register */ -#define PIOD_PER (0xa00) /* PIO Enable Register */ -#define PIOD_PDR (0xa00 + 4) /* PIO Disable Register */ -#define PIOD_PSR (0xa00 + 8) /* PIO status register */ -#define PIOD_OER (0xa00 + 16) /* Output enable register */ -#define PIOD_ODR (0xa00 + 20) /* Output disable register */ -#define PIOD_OSR (0xa00 + 24) /* Output status register */ -#define PIOD_IFER (0xa00 + 32) /* Input filter enable register */ -#define PIOD_IFDR (0xa00 + 36) /* Input filter disable register */ -#define PIOD_IFSR (0xa00 + 40) /* Input filter status register */ -#define PIOD_SODR (0xa00 + 48) /* Set output data register */ -#define PIOD_CODR (0xa00 + 52) /* Clear output data register */ -#define PIOD_ODSR (0xa00 + 56) /* Output data status register */ -#define PIOD_PDSR (0xa00 + 60) /* Pin data status register */ -#define PIOD_IER (0xa00 + 64) /* Interrupt enable register */ -#define PIOD_IDR (0xa00 + 68) /* Interrupt disable register */ -#define PIOD_IMR (0xa00 + 72) /* Interrupt mask register */ -#define PIOD_ISR (0xa00 + 76) /* Interrupt status register */ -#define PIOD_MDER (0xa00 + 80) /* Multi driver enable register */ -#define PIOD_MDDR (0xa00 + 84) /* Multi driver disable register */ -#define PIOD_MDSR (0xa00 + 88) /* Multi driver status register */ -#define PIOD_PPUDR (0xa00 + 96) /* Pull-up disable register */ -#define PIOD_PPUER (0xa00 + 100) /* Pull-up enable register */ -#define PIOD_PPUSR (0xa00 + 104) /* Pad pull-up status register */ -#define PIOD_ASR (0xa00 + 112) /* Select A register */ -#define PIOD_BSR (0xa00 + 116) /* Select B register */ -#define PIOD_ABSR (0xa00 + 120) /* AB Select status register */ -#define PIOD_OWER (0xa00 + 160) /* Output Write enable register */ -#define PIOD_OWDR (0xa00 + 164) /* Output write disable register */ -#define PIOD_OWSR (0xa00 + 168) /* Output write status register */ - -#endif /* * PIO */