Date: Thu, 12 Feb 2015 21:10:25 +0000 (UTC) From: Ian Lepore <ian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r278635 - in stable/10/sys: arm/arm arm/include conf Message-ID: <201502122110.t1CLAPuk004481@svn.freebsd.org>
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Author: ian Date: Thu Feb 12 21:10:24 2015 New Revision: 278635 URL: https://svnweb.freebsd.org/changeset/base/278635 Log: MFC r276247, r276333, r276334, r276335, r276336, r276340, r276350: Include acle-compat.h directly rather than getting it via sysreg.h. Add new code to read and parse cpu identification data using the new CPUID mechanism defined for armv7. Add new TLB and cache maintainence functions for armv6 and armv7. Eliminate an unused macro whose name clashes now with a function in the new cpu-v6.h Add cache maintenance functions which will be used by startup code to initially set up the MMU. Fix a "decl is not a prototype" error noticed by gcc (but not clang). Update comments (r4 is not used anywhere), use non-profiling entry macros. Add arm option ARM_NEW_PMAP, to allow us to begin adding the new pmap code alongside the existing implementation Add armv6 implementations of cache operations to avoid duplication Added: stable/10/sys/arm/arm/cpu_asm-v6.S - copied, changed from r276336, head/sys/arm/arm/cpu_asm-v6.S stable/10/sys/arm/arm/cpuinfo.c - copied unchanged from r276333, head/sys/arm/arm/cpuinfo.c stable/10/sys/arm/include/cpu-v6.h - copied, changed from r276333, head/sys/arm/include/cpu-v6.h stable/10/sys/arm/include/cpuinfo.h - copied unchanged from r276333, head/sys/arm/include/cpuinfo.h Modified: stable/10/sys/arm/arm/machdep.c stable/10/sys/arm/include/asm.h stable/10/sys/arm/include/cpufunc.h stable/10/sys/conf/files.arm Directory Properties: stable/10/ (props changed) Copied and modified: stable/10/sys/arm/arm/cpu_asm-v6.S (from r276336, head/sys/arm/arm/cpu_asm-v6.S) ============================================================================== --- head/sys/arm/arm/cpu_asm-v6.S Sun Dec 28 18:38:25 2014 (r276336, copy source) +++ stable/10/sys/arm/arm/cpu_asm-v6.S Thu Feb 12 21:10:24 2015 (r278635) @@ -37,14 +37,16 @@ /* * Define cache functions used by startup code, which counts on the fact that - * only r0-r4,r12 (ip) are modified and no stack space is used. This set - * of function must be called with interrupts disabled and don't follow - * ARM ABI (cannot be called form C code. - * Moreover, it works only with caches integrated to CPU (accessible via CP15). + * only r0-r3,r12 (ip) are modified and no stack space is used. These functions + * must be called with interrupts disabled. Moreover, these work only with + * caches integrated to CPU (accessible via CP15); systems with an external L2 + * cache controller such as a PL310 need separate calls to that device driver + * to affect L2 caches. This is not a factor during early kernel startup, as + * any external L2 cache controller has not been enabled yet. */ /* Invalidate D cache to PoC. (aka all cache levels)*/ -ASENTRY(dcache_inv_poc_all) +ASENTRY_NP(dcache_inv_poc_all) mrc CP15_CLIDR(r0) ands r0, r0, #0x07000000 mov r0, r0, lsr #23 /* Get LoC (naturally aligned) */ @@ -96,7 +98,7 @@ ASENTRY(dcache_inv_poc_all) END(dcache_inv_poc_all) /* Invalidate D cache to PoU. (aka L1 cache only)*/ -ASENTRY(dcache_inv_pou_all) +ASENTRY_NP(dcache_inv_pou_all) mrc CP15_CLIDR(r0) ands r0, r0, #0x07000000 mov r0, r0, lsr #26 /* Get LoUU (naturally aligned) */ @@ -147,7 +149,7 @@ ASENTRY(dcache_inv_pou_all) END(dcache_inv_pou_all) /* Write back and Invalidate D cache to PoC. */ -ASENTRY(dcache_wbinv_poc_all) +ASENTRY_NP(dcache_wbinv_poc_all) mrc CP15_CLIDR(r0) ands r0, r0, #0x07000000 mov r0, r0, lsr #23 /* Get LoC (naturally aligned) */ Copied: stable/10/sys/arm/arm/cpuinfo.c (from r276333, head/sys/arm/arm/cpuinfo.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ stable/10/sys/arm/arm/cpuinfo.c Thu Feb 12 21:10:24 2015 (r278635, copy of r276333, head/sys/arm/arm/cpuinfo.c) @@ -0,0 +1,121 @@ +/*- + * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> + * Copyright 2014 Michal Meloun <meloun@miracle.cz> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> + +#include <machine/cpuinfo.h> +#include <machine/cpu-v6.h> + +struct cpuinfo cpuinfo; + +/* Read and parse CPU id scheme */ +void +cpuinfo_init(void) +{ + + cpuinfo.midr = cp15_midr_get(); + /* Test old version id schemes first */ + if ((cpuinfo.midr & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD) { + if (CPU_ID_ISOLD(cpuinfo.midr)) { + /* obsolete ARMv2 or ARMv3 CPU */ + cpuinfo.midr = 0; + return; + } + if (CPU_ID_IS7(cpuinfo.midr)) { + if ((cpuinfo.midr & (1 << 23)) == 0) { + /* obsolete ARMv3 CPU */ + cpuinfo.midr = 0; + return; + } + /* ARMv4T CPU */ + cpuinfo.architecture = 1; + cpuinfo.revision = (cpuinfo.midr >> 16) & 0x7F; + } + } else { + /* must be new id scheme */ + cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F; + cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F; + } + /* Parse rest of MIDR */ + cpuinfo.implementer = (cpuinfo.midr >> 24) & 0xFF; + cpuinfo.part_number = (cpuinfo.midr >> 4) & 0xFFF; + cpuinfo.patch = cpuinfo.midr & 0x0F; + + /* CP15 c0,c0 regs 0-7 exist on all CPUs (although aliased with MIDR) */ + cpuinfo.ctr = cp15_ctr_get(); + cpuinfo.tcmtr = cp15_tcmtr_get(); + cpuinfo.tlbtr = cp15_tlbtr_get(); + cpuinfo.mpidr = cp15_mpidr_get(); + cpuinfo.revidr = cp15_revidr_get(); + + /* if CPU is not v7 cpu id scheme */ + if (cpuinfo.architecture != 0xF) + return; + + cpuinfo.id_pfr0 = cp15_id_pfr0_get(); + cpuinfo.id_pfr1 = cp15_id_pfr1_get(); + cpuinfo.id_dfr0 = cp15_id_dfr0_get(); + cpuinfo.id_afr0 = cp15_id_afr0_get(); + cpuinfo.id_mmfr0 = cp15_id_mmfr0_get(); + cpuinfo.id_mmfr1 = cp15_id_mmfr1_get(); + cpuinfo.id_mmfr2 = cp15_id_mmfr2_get(); + cpuinfo.id_mmfr3 = cp15_id_mmfr3_get(); + cpuinfo.id_isar0 = cp15_id_isar0_get(); + cpuinfo.id_isar1 = cp15_id_isar1_get(); + cpuinfo.id_isar2 = cp15_id_isar2_get(); + cpuinfo.id_isar3 = cp15_id_isar3_get(); + cpuinfo.id_isar4 = cp15_id_isar4_get(); + cpuinfo.id_isar5 = cp15_id_isar5_get(); + +/* Not yet - CBAR only exist on ARM SMP Cortex A CPUs + cpuinfo.cbar = cp15_cbar_get(); +*/ + + /* Test if revidr is implemented */ + if (cpuinfo.revidr == cpuinfo.midr) + cpuinfo.revidr = 0; + + /* parsed bits of above registers */ + /* id_mmfr0 */ + cpuinfo.outermost_shareability = (cpuinfo.id_mmfr0 >> 8) & 0xF; + cpuinfo.shareability_levels = (cpuinfo.id_mmfr0 >> 12) & 0xF; + cpuinfo.auxiliary_registers = (cpuinfo.id_mmfr0 >> 20) & 0xF; + cpuinfo.innermost_shareability = (cpuinfo.id_mmfr0 >> 28) & 0xF; + /* id_mmfr2 */ + cpuinfo.mem_barrier = (cpuinfo.id_mmfr2 >> 20) & 0xF; + /* id_mmfr3 */ + cpuinfo.coherent_walk = (cpuinfo.id_mmfr3 >> 20) & 0xF; + cpuinfo.maintenance_broadcast =(cpuinfo.id_mmfr3 >> 12) & 0xF; + /* id_pfr1 */ + cpuinfo.generic_timer_ext = (cpuinfo.id_pfr1 >> 16) & 0xF; + cpuinfo.virtualization_ext = (cpuinfo.id_pfr1 >> 12) & 0xF; + cpuinfo.security_ext = (cpuinfo.id_pfr1 >> 4) & 0xF; +} Modified: stable/10/sys/arm/arm/machdep.c ============================================================================== --- stable/10/sys/arm/arm/machdep.c Thu Feb 12 21:07:42 2015 (r278634) +++ stable/10/sys/arm/arm/machdep.c Thu Feb 12 21:10:24 2015 (r278635) @@ -90,6 +90,7 @@ __FBSDID("$FreeBSD$"); #include <machine/armreg.h> #include <machine/atags.h> #include <machine/cpu.h> +#include <machine/cpuinfo.h> #include <machine/devmap.h> #include <machine/frame.h> #include <machine/intr.h> @@ -1058,6 +1059,8 @@ initarm(struct arm_boot_params *abp) arm_physmem_kernaddr = abp->abp_physaddr; memsize = 0; + + cpuinfo_init(); set_cpufuncs(); /* Modified: stable/10/sys/arm/include/asm.h ============================================================================== --- stable/10/sys/arm/include/asm.h Thu Feb 12 21:07:42 2015 (r278634) +++ stable/10/sys/arm/include/asm.h Thu Feb 12 21:10:24 2015 (r278635) @@ -39,6 +39,7 @@ #ifndef _MACHINE_ASM_H_ #define _MACHINE_ASM_H_ #include <sys/cdefs.h> +#include <machine/acle-compat.h> #include <machine/sysreg.h> #define _C_LABEL(x) x Copied and modified: stable/10/sys/arm/include/cpu-v6.h (from r276333, head/sys/arm/include/cpu-v6.h) ============================================================================== --- head/sys/arm/include/cpu-v6.h Sun Dec 28 18:12:56 2014 (r276333, copy source) +++ stable/10/sys/arm/include/cpu-v6.h Thu Feb 12 21:10:24 2015 (r278635) @@ -155,4 +155,242 @@ _RF0(cp15_cbar_get, CP15_CBAR(%0)) #undef _WF0 #undef _WF1 +/* + * TLB maintenance operations. + */ + +/* Local (i.e. not broadcasting ) operations. */ + +/* Flush all TLB entries (even global). */ +static __inline void +tlb_flush_all_local(void) +{ + + dsb(); + _CP15_TLBIALL(); + dsb(); +} + +/* Flush all not global TLB entries. */ +static __inline void +tlb_flush_all_ng_local(void) +{ + + dsb(); + _CP15_TLBIASID(CPU_ASID_KERNEL); + dsb(); +} + +/* Flush single TLB entry (even global). */ +static __inline void +tlb_flush_local(vm_offset_t sva) +{ + + dsb(); + _CP15_TLBIMVA((sva & ~PAGE_MASK ) | CPU_ASID_KERNEL); + dsb(); +} + +/* Flush range of TLB entries (even global). */ +static __inline void +tlb_flush_range_local(vm_offset_t sva, vm_size_t size) +{ + vm_offset_t va; + vm_offset_t eva = sva + size; + + dsb(); + for (va = sva; va < eva; va += PAGE_SIZE) + _CP15_TLBIMVA((va & ~PAGE_MASK ) | CPU_ASID_KERNEL); + dsb(); +} + +/* Broadcasting operations. */ +#ifndef SMP + +#define tlb_flush_all() tlb_flush_all_local() +#define tlb_flush_all_ng() tlb_flush_all_ng_local() +#define tlb_flush(sva) tlb_flush_local(sva) +#define tlb_flush_range(sva, size) tlb_flush_range_local(sva, size) + +#else /* SMP */ + +static __inline void +tlb_flush_all(void) +{ + + dsb(); + _CP15_TLBIALLIS(); + dsb(); +} + +static __inline void +tlb_flush_all_ng(void) +{ + + dsb(); + _CP15_TLBIASIDIS(CPU_ASID_KERNEL); + dsb(); +} + +static __inline void +tlb_flush(vm_offset_t sva) +{ + + dsb(); + _CP15_TLBIMVAAIS(sva); + dsb(); +} + +static __inline void +tlb_flush_range(vm_offset_t sva, vm_size_t size) +{ + vm_offset_t va; + vm_offset_t eva = sva + size; + + dsb(); + for (va = sva; va < eva; va += PAGE_SIZE) + _CP15_TLBIMVAAIS(va); + dsb(); +} +#endif /* SMP */ + +/* + * Cache maintenance operations. + */ + +/* Sync I and D caches to PoU */ +static __inline void +icache_sync(vm_offset_t sva, vm_size_t size) +{ + vm_offset_t va; + vm_offset_t eva = sva + size; + + dsb(); + for (va = sva; va < eva; va += arm_dcache_align) { +#ifdef SMP + _CP15_DCCMVAU(va); +#else + _CP15_DCCMVAC(va); +#endif + } + dsb(); +#ifdef SMP + _CP15_ICIALLUIS(); +#else + _CP15_ICIALLU(); +#endif + dsb(); + isb(); +} + +/* Invalidate I cache */ +static __inline void +icache_inv_all(void) +{ +#ifdef SMP + _CP15_ICIALLUIS(); +#else + _CP15_ICIALLU(); +#endif + dsb(); + isb(); +} + +/* Write back D-cache to PoU */ +static __inline void +dcache_wb_pou(vm_offset_t sva, vm_size_t size) +{ + vm_offset_t va; + vm_offset_t eva = sva + size; + + dsb(); + for (va = sva; va < eva; va += arm_dcache_align) { +#ifdef SMP + _CP15_DCCMVAU(va); +#else + _CP15_DCCMVAC(va); +#endif + } + dsb(); +} + +/* Invalidate D-cache to PoC */ +static __inline void +dcache_inv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size) +{ + vm_offset_t va; + vm_offset_t eva = sva + size; + + /* invalidate L1 first */ + for (va = sva; va < eva; va += arm_dcache_align) { + _CP15_DCIMVAC(va); + } + dsb(); + + /* then L2 */ + cpu_l2cache_inv_range(pa, size); + dsb(); + + /* then L1 again */ + for (va = sva; va < eva; va += arm_dcache_align) { + _CP15_DCIMVAC(va); + } + dsb(); +} + +/* Write back D-cache to PoC */ +static __inline void +dcache_wb_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size) +{ + vm_offset_t va; + vm_offset_t eva = sva + size; + + dsb(); + + for (va = sva; va < eva; va += arm_dcache_align) { + _CP15_DCCMVAC(va); + } + dsb(); + + cpu_l2cache_wb_range(pa, size); +} + +/* Write back and invalidate D-cache to PoC */ +static __inline void +dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size) +{ + vm_offset_t va; + vm_offset_t eva = sva + size; + + dsb(); + + /* write back L1 first */ + for (va = sva; va < eva; va += arm_dcache_align) { + _CP15_DCCMVAC(va); + } + dsb(); + + /* then write back and invalidate L2 */ + cpu_l2cache_wbinv_range(pa, size); + + /* then invalidate L1 */ + for (va = sva; va < eva; va += arm_dcache_align) { + _CP15_DCIMVAC(va); + } + dsb(); +} + +/* Set TTB0 register */ +static __inline void +cp15_ttbr_set(uint32_t reg) +{ + dsb(); + _CP15_TTB_SET(reg); + dsb(); + _CP15_BPIALL(); + dsb(); + isb(); + tlb_flush_all_ng_local(); +} + #endif /* !MACHINE_CPU_V6_H */ Modified: stable/10/sys/arm/include/cpufunc.h ============================================================================== --- stable/10/sys/arm/include/cpufunc.h Thu Feb 12 21:07:42 2015 (r278634) +++ stable/10/sys/arm/include/cpufunc.h Thu Feb 12 21:10:24 2015 (r278635) @@ -572,7 +572,6 @@ void xscalec3_context_switch (void); #endif /* CPU_XSCALE_81342 */ -#define tlb_flush cpu_tlb_flushID #define setttb cpu_setttb #define drain_writebuf cpu_drain_writebuf Copied: stable/10/sys/arm/include/cpuinfo.h (from r276333, head/sys/arm/include/cpuinfo.h) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ stable/10/sys/arm/include/cpuinfo.h Thu Feb 12 21:10:24 2015 (r278635, copy of r276333, head/sys/arm/include/cpuinfo.h) @@ -0,0 +1,91 @@ +/*- + * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> + * Copyright 2014 Michal Meloun <meloun@miracle.cz> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_CPUINFO_H_ +#define _MACHINE_CPUINFO_H_ + +#include <sys/types.h> + +struct cpuinfo { + /* raw id registers */ + uint32_t midr; + uint32_t ctr; + uint32_t tcmtr; + uint32_t tlbtr; + uint32_t mpidr; + uint32_t revidr; + uint32_t id_pfr0; + uint32_t id_pfr1; + uint32_t id_dfr0; + uint32_t id_afr0; + uint32_t id_mmfr0; + uint32_t id_mmfr1; + uint32_t id_mmfr2; + uint32_t id_mmfr3; + uint32_t id_isar0; + uint32_t id_isar1; + uint32_t id_isar2; + uint32_t id_isar3; + uint32_t id_isar4; + uint32_t id_isar5; + uint32_t cbar; + + /* Parsed bits of above registers... */ + + /* midr */ + int implementer; + int revision; + int architecture; + int part_number; + int patch; + + /* id_mmfr0 */ + int outermost_shareability; + int shareability_levels; + int auxiliary_registers; + int innermost_shareability; + + /* id_mmfr1 */ + int mem_barrier; + + /* id_mmfr3 */ + int coherent_walk; + int maintenance_broadcast; + + /* id_pfr1 */ + int generic_timer_ext; + int virtualization_ext; + int security_ext; +}; + +extern struct cpuinfo cpuinfo; + +void cpuinfo_init(void); + +#endif /* _MACHINE_CPUINFO_H_ */ Modified: stable/10/sys/conf/files.arm ============================================================================== --- stable/10/sys/conf/files.arm Thu Feb 12 21:07:42 2015 (r278634) +++ stable/10/sys/conf/files.arm Thu Feb 12 21:10:24 2015 (r278635) @@ -11,6 +11,8 @@ arm/arm/copystr.S standard arm/arm/cpufunc.c standard arm/arm/cpufunc_asm.S standard arm/arm/cpufunc_asm_armv4.S standard +arm/arm/cpuinfo.c standard +arm/arm/cpu_asm-v6.S optional armv6 arm/arm/db_disasm.c optional ddb arm/arm/db_interface.c optional ddb arm/arm/db_trace.c optional ddb
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