From owner-svn-src-all@freebsd.org Sat May 14 23:20:48 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 1EC3EB3B786; Sat, 14 May 2016 23:20:48 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id D3CF11D97; Sat, 14 May 2016 23:20:47 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u4ENKlTH081741; Sat, 14 May 2016 23:20:47 GMT (envelope-from adrian@FreeBSD.org) Received: (from adrian@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u4ENKkQw081738; Sat, 14 May 2016 23:20:46 GMT (envelope-from adrian@FreeBSD.org) Message-Id: <201605142320.u4ENKkQw081738@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: adrian set sender to adrian@FreeBSD.org using -f From: Adrian Chadd Date: Sat, 14 May 2016 23:20:46 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r299776 - head/sys/dev/bwn X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 May 2016 23:20:48 -0000 Author: adrian Date: Sat May 14 23:20:46 2016 New Revision: 299776 URL: https://svnweb.freebsd.org/changeset/base/299776 Log: [bwn] implement reset improvements in preparation for PHY-N support * Ensure we set 20MHz wide channels (hard-coded) for PHY-N. * Change the core rese tto take a flag saying "gmode" vesus uint32_t flags. This is important for BCMA support where the "gmode" bit is different. * Refactor out the mac-phy clock reset routine (usde by PHY-N). Tested: * BCM4321 (PHY-N), BCM4312 (PHY-LP) TODO: * Checkpoint test on PHY-G hardware, just to check. Modified: head/sys/dev/bwn/if_bwn.c head/sys/dev/bwn/if_bwn_misc.h head/sys/dev/bwn/if_bwn_phy_g.c Modified: head/sys/dev/bwn/if_bwn.c ============================================================================== --- head/sys/dev/bwn/if_bwn.c Sat May 14 23:13:44 2016 (r299775) +++ head/sys/dev/bwn/if_bwn.c Sat May 14 23:20:46 2016 (r299776) @@ -77,6 +77,8 @@ __FBSDID("$FreeBSD$"); #include #include +#include +#include #include #include @@ -1142,8 +1144,7 @@ bwn_attach_core(struct bwn_mac *mac) siba_powerup(sc->sc_dev, 0); high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH); - bwn_reset_core(mac, - (high & BWN_TGSHIGH_HAVE_2GHZ) ? BWN_TGSLOW_SUPPORT_G : 0); + bwn_reset_core(mac, !!(high & BWN_TGSHIGH_HAVE_2GHZ)); error = bwn_phy_getinfo(mac, high); if (error) goto fail; @@ -1223,7 +1224,7 @@ bwn_attach_core(struct bwn_mac *mac) } } - bwn_reset_core(mac, have_bg ? BWN_TGSLOW_SUPPORT_G : 0); + bwn_reset_core(mac, have_bg); error = bwn_chiptest(mac); if (error) @@ -1251,17 +1252,32 @@ fail: return (error); } +/* + * Reset - SIBA. + * + * XXX TODO: implement BCMA version! + */ void -bwn_reset_core(struct bwn_mac *mac, uint32_t flags) +bwn_reset_core(struct bwn_mac *mac, int g_mode) { struct bwn_softc *sc = mac->mac_sc; uint32_t low, ctl; + uint32_t flags = 0; + + DPRINTF(sc, BWN_DEBUG_RESET, "%s: g_mode=%d\n", __func__, g_mode); flags |= (BWN_TGSLOW_PHYCLOCK_ENABLE | BWN_TGSLOW_PHYRESET); + if (g_mode) + flags |= BWN_TGSLOW_SUPPORT_G; + + /* XXX N-PHY only; and hard-code to 20MHz for now */ + if (mac->mac_phy.type == BWN_PHYTYPE_N) + flags |= BWN_TGSLOW_PHY_BANDWIDTH_20MHZ; siba_dev_up(sc->sc_dev, flags); DELAY(2000); + /* Take PHY out of reset */ low = (siba_read_4(sc->sc_dev, SIBA_TGSLOW) | SIBA_TGSLOW_FGC) & ~BWN_TGSLOW_PHYRESET; siba_write_4(sc->sc_dev, SIBA_TGSLOW, low); @@ -1275,7 +1291,7 @@ bwn_reset_core(struct bwn_mac *mac, uint mac->mac_phy.switch_analog(mac, 1); ctl = BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GMODE; - if (flags & BWN_TGSLOW_SUPPORT_G) + if (g_mode) ctl |= BWN_MACCTL_GMODE; BWN_WRITE_4(mac, BWN_MACCTL, ctl | BWN_MACCTL_IHR_ON); } @@ -1289,7 +1305,7 @@ bwn_phy_getinfo(struct bwn_mac *mac, int /* PHY */ tmp = BWN_READ_2(mac, BWN_PHYVER); - phy->gmode = (tgshigh & BWN_TGSHIGH_HAVE_2GHZ) ? 1 : 0; + phy->gmode = !! (tgshigh & BWN_TGSHIGH_HAVE_2GHZ); phy->rf_on = 1; phy->analog = (tmp & BWN_PHYVER_ANALOG) >> 12; phy->type = (tmp & BWN_PHYVER_TYPE) >> 8; @@ -1945,8 +1961,7 @@ bwn_core_init(struct bwn_mac *mac) siba_powerup(sc->sc_dev, 0); if (!siba_dev_isup(sc->sc_dev)) - bwn_reset_core(mac, - mac->mac_phy.gmode ? BWN_TGSLOW_SUPPORT_G : 0); + bwn_reset_core(mac, mac->mac_phy.gmode); mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID; mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON; @@ -2175,8 +2190,11 @@ bwn_chip_init(struct bwn_mac *mac) BWN_WRITE_4(mac, BWN_DMA3_INTR_MASK, 0x0001dc00); BWN_WRITE_4(mac, BWN_DMA4_INTR_MASK, 0x0000dc00); BWN_WRITE_4(mac, BWN_DMA5_INTR_MASK, 0x0000dc00); - siba_write_4(sc->sc_dev, SIBA_TGSLOW, - siba_read_4(sc->sc_dev, SIBA_TGSLOW) | 0x00100000); + + bwn_mac_phy_clock_set(mac, true); + + /* SIBA powerup */ + /* XXX TODO: BCMA powerup */ BWN_WRITE_2(mac, BWN_POWERUP_DELAY, siba_get_cc_powerdelay(sc->sc_dev)); return (error); } @@ -4495,6 +4513,11 @@ bwn_rf_turnoff(struct bwn_mac *mac) bwn_mac_enable(mac); } +/* + * SSB PHY reset. + * + * XXX TODO: BCMA PHY reset. + */ static void bwn_phy_reset(struct bwn_mac *mac) { @@ -4505,8 +4528,7 @@ bwn_phy_reset(struct bwn_mac *mac) BWN_TGSLOW_PHYRESET) | SIBA_TGSLOW_FGC); DELAY(1000); siba_write_4(sc->sc_dev, SIBA_TGSLOW, - (siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~SIBA_TGSLOW_FGC) | - BWN_TGSLOW_PHYRESET); + (siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~SIBA_TGSLOW_FGC)); DELAY(1000); } Modified: head/sys/dev/bwn/if_bwn_misc.h ============================================================================== --- head/sys/dev/bwn/if_bwn_misc.h Sat May 14 23:13:44 2016 (r299775) +++ head/sys/dev/bwn/if_bwn_misc.h Sat May 14 23:20:46 2016 (r299776) @@ -59,7 +59,9 @@ extern uint32_t bwn_shm_read_4(struct bw extern void bwn_shm_write_4(struct bwn_mac *, uint16_t, uint16_t, uint32_t); -extern void bwn_reset_core(struct bwn_mac *, uint32_t); +/* This is only for SIBA core */ +extern void bwn_reset_core(struct bwn_mac *, int g_mode); + extern void bwn_psctl(struct bwn_mac *, uint32_t); #endif Modified: head/sys/dev/bwn/if_bwn_phy_g.c ============================================================================== --- head/sys/dev/bwn/if_bwn_phy_g.c Sat May 14 23:13:44 2016 (r299775) +++ head/sys/dev/bwn/if_bwn_phy_g.c Sat May 14 23:20:46 2016 (r299776) @@ -418,7 +418,7 @@ genbbatt: bwn_reset_core(mac, 0); bwn_phy_g_init_sub(mac); phy->gmode = 1; - bwn_reset_core(mac, BWN_TGSLOW_SUPPORT_G); + bwn_reset_core(mac, 1); } return (0); }