From owner-freebsd-current@FreeBSD.ORG Fri Aug 1 18:48:49 2014 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 1ED5ACAE for ; Fri, 1 Aug 2014 18:48:49 +0000 (UTC) Received: from mail-wi0-x22f.google.com (mail-wi0-x22f.google.com [IPv6:2a00:1450:400c:c05::22f]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G2" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id A711E268E for ; Fri, 1 Aug 2014 18:48:48 +0000 (UTC) Received: by mail-wi0-f175.google.com with SMTP id ho1so1852728wib.14 for ; Fri, 01 Aug 2014 11:48:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:subject:references :in-reply-to:content-type; bh=y7tFhVGU51yVVz9c+qDhRRhSnpPTShf/XN18x+NlfKo=; b=ndmxqtQFxaK/sBUVPP68K8xE1AbX0sUmWuTb7EHwscK+elxJ6FUlnv6X5ymc9A/otR ULhqov0QEC8hUxvQ2rL5XNi5P/u6o5PbedTaU5wo+6eXBu+GywO7FAJSsgOjJE52amo6 EI72u68FAW8vZAOl3EBnuAEoI5ibuuOytCguow08XG1KL7iQsqtouNsQKG2yd1qyO/sN 4He+LTSE8m9eQNmA2F/FYtAj48V8vS/luJfzKUqB4+z5ZUUTDD8dRaKeJ/GX2m/Fov5l flr8LZZSRMtqs3ukicvtkL48rCodWiwXS3ai1VQqpfJInPKy+pRdueNwMjY9ZY/bxeB/ UB8Q== X-Received: by 10.194.219.225 with SMTP id pr1mr10960160wjc.34.1406918926242; Fri, 01 Aug 2014 11:48:46 -0700 (PDT) Received: from [192.168.178.122] (p5B36F3D4.dip0.t-ipconnect.de. [91.54.243.212]) by mx.google.com with ESMTPSA id f16sm11212618wic.7.2014.08.01.11.48.44 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 01 Aug 2014 11:48:45 -0700 (PDT) Message-ID: <53DBE10B.9010202@gmail.com> Date: Fri, 01 Aug 2014 20:48:43 +0200 From: =?ISO-8859-1?Q?Jan_Kokem=FCller?= User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 To: freebsd-current@freebsd.org Subject: Re: Fresh current (r269328) amd64: high load average while idle, slow keyboard reaction References: <20140731142100.GP92036@heechee.tobez.org> <53DA6727.7080702@gmail.com> In-Reply-To: <53DA6727.7080702@gmail.com> Content-Type: multipart/mixed; boundary="------------080104080403040701080004" X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Aug 2014 18:48:49 -0000 This is a multi-part message in MIME format. --------------080104080403040701080004 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Hi, > Maybe this is a problem caused by a misdetected clock source? I've had > this problem as well. I've appended the patch I've been using to fix this problem on this Intel Core2Duo T6570 processor. There are some model IDs hardcoded in the TSC detection code that enable TSC even though it's not invariant here (no TSC_INVARIANT bit set on the CPU). There is some quirk code further down that disables TSC once again, but it only works for processors that have C3 power states (the T6570 doesn't). I don't think any of this model checking code is necessary, but maybe I'm wrong. Cheers, Jan --------------080104080403040701080004 Content-Type: text/x-patch; name="fix-invariant-tsc-detection.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="fix-invariant-tsc-detection.patch" diff --git a/sys/x86/x86/tsc.c b/sys/x86/x86/tsc.c index 2a6c81d..a30424e 100644 --- a/sys/x86/x86/tsc.c +++ b/sys/x86/x86/tsc.c @@ -57,7 +57,8 @@ int tsc_perf_stat; static eventhandler_tag tsc_levels_tag, tsc_pre_tag, tsc_post_tag; SYSCTL_INT(_kern_timecounter, OID_AUTO, invariant_tsc, CTLFLAG_RDTUN, - &tsc_is_invariant, 0, "Indicates whether the TSC is P-state invariant"); + &tsc_is_invariant, 0, + "Indicates whether the TSC is ACPI P-, C- and T-state invariant"); TUNABLE_INT("kern.timecounter.invariant_tsc", &tsc_is_invariant); #ifdef SMP @@ -272,9 +273,7 @@ probe_tsc_freq(void) switch (cpu_vendor_id) { case CPU_VENDOR_AMD: - if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 || - (vm_guest == VM_GUEST_NO && - CPUID_TO_FAMILY(cpu_id) >= 0x10)) + if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0) tsc_is_invariant = 1; if (cpu_feature & CPUID_SSE2) { tsc_timecounter.tc_get_timecount = @@ -282,12 +281,7 @@ probe_tsc_freq(void) } break; case CPU_VENDOR_INTEL: - if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 || - (vm_guest == VM_GUEST_NO && - ((CPUID_TO_FAMILY(cpu_id) == 0x6 && - CPUID_TO_MODEL(cpu_id) >= 0xe) || - (CPUID_TO_FAMILY(cpu_id) == 0xf && - CPUID_TO_MODEL(cpu_id) >= 0x3)))) + if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0) tsc_is_invariant = 1; if (cpu_feature & CPUID_SSE2) { tsc_timecounter.tc_get_timecount = @@ -554,20 +548,6 @@ init_TSC_tc(void) } /* - * We cannot use the TSC if it stops incrementing in deep sleep. - * Currently only Intel CPUs are known for this problem unless - * the invariant TSC bit is set. - */ - if (cpu_can_deep_sleep && cpu_vendor_id == CPU_VENDOR_INTEL && - (amd_pminfo & AMDPM_TSC_INVARIANT) == 0) { - tsc_timecounter.tc_quality = -1000; - tsc_timecounter.tc_flags |= TC_FLAGS_C3STOP; - if (bootverbose) - printf("TSC timecounter disabled: C3 enabled.\n"); - goto init; - } - - /* * We can not use the TSC in SMP mode unless the TSCs on all CPUs * are synchronized. If the user is sure that the system has * synchronized TSCs, set kern.timecounter.smp_tsc tunable to a --------------080104080403040701080004--