Date: Wed, 20 Feb 2008 23:30:00 -0700 (MST) From: "M. Warner Losh" <imp@bsdimp.com> To: mcc@fid4.com Cc: freebsd-mobile@freebsd.org Subject: Re: FreeBSD 7 doesn't see AR5212 (Netgear WPN511) via PCI/Cardbus Adapter Message-ID: <20080220.233000.1021575865.imp@bsdimp.com> In-Reply-To: <47BC859F.6050603@fid4.com> References: <47BC7B3D.9020804@fid4.com> <47BC7D9D.3010707@errno.com> <47BC859F.6050603@fid4.com>
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In message: <47BC859F.6050603@fid4.com> "Michael C. Cambria" <mcc@fid4.com> writes: : Sam Leffler wrote: : > : > You chopped too much context so I cannot tell what you're referring : > too. I can only say that I have a T42 running HEAD that doesn't : > recognize an Atheros cardbus card I have. The same card works in : > another thinkpad w/ a different cardbus chip. The card works under : > other OS's on the T42 so it's a regression in HEAD (and likely 7.0). : > : > I traced through the code and think I pinned it down to not powering : > on the card on insert but am not certain. : > : > Sam : : As Warner said, I think there are two issues. : : To rule out pilot error, I now test with both the 6.3 and 7.0 from disk : 1 of the install CD's. Both have ath compiled in. : : Booting from a laptop, ath is seen just fine. I use sysinstall to : configure ath, enter a shell and play with ifconfig etc. : : When I boot on the system that has the pci->cardbus adapter, ath isn't : detected at all. On this same system, my 802.11b (wi0) cards are : detected just fine. Please try this patch and send me the results of 'sysctl dev.pci' and 'sysctl dev.pcib' and 'sysctl dev.cbb'. There's 0 chance it will fix the problem, but will let us know for sure if this is my 'problem 1' or something else. This patch is against today's -current, but may apply, maybe with some fuzz, to earlier versions. Warner Index: pci_if.m =================================================================== RCS file: /cache/ncvs/src/sys/dev/pci/pci_if.m,v retrieving revision 1.12 diff -u -r1.12 pci_if.m --- pci_if.m 2 May 2007 17:50:35 -0000 1.12 +++ pci_if.m 10 May 2007 02:36:02 -0000 @@ -145,3 +145,10 @@ device_t dev; device_t child; } DEFAULT null_msi_count; + +METHOD int alloc_bus { + device_t dev; + device_t child; + int num; + int *bus; +}; Index: pci_pci.c =================================================================== RCS file: /cache/ncvs/src/sys/dev/pci/pci_pci.c,v retrieving revision 1.50 diff -u -r1.50 pci_pci.c --- pci_pci.c 30 Sep 2007 11:05:15 -0000 1.50 +++ pci_pci.c 21 Feb 2008 01:42:40 -0000 @@ -139,6 +139,8 @@ { struct pcib_softc *sc; uint8_t iolow; + struct sysctl_ctx_list *sctx; + struct sysctl_oid *soid; sc = device_get_softc(dev); sc->dev = dev; @@ -153,6 +155,19 @@ sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); + sc->pribus = pcib_get_bus(device_get_parent(dev)); + + /*Sysctls*/ + sctx = device_get_sysctl_ctx(dev); + soid = device_get_sysctl_tree(dev); + SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", + CTLFLAG_RD, &sc->domain, 0, "Domain number"); + SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", + CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); + SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", + CTLFLAG_RD, &sc->secbus, 0, "Secondary bus number"); + SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", + CTLFLAG_RD, &sc->subbus, 0, "Subordinate bus number"); /* * Determine current I/O decode. @@ -258,10 +273,11 @@ sc->flags |= PCIB_SUBTRACTIVE; if (bootverbose) { - device_printf(dev, " domain %d\n", sc->domain); - device_printf(dev, " secondary bus %d\n", sc->secbus); - device_printf(dev, " subordinate bus %d\n", sc->subbus); - device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); + device_printf(dev, " domain %ld\n", (long)sc->domain); + device_printf(dev, " secondary bus %ld\n", (long)sc->secbus); + device_printf(dev, " subordinate bus %ld\n", (long)sc->subbus); + device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, + sc->iolimit); if (pcib_is_nonprefetch_open(sc)) device_printf(dev, " memory decode 0x%jx-0x%jx\n", (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); Index: pcib_private.h =================================================================== RCS file: /cache/ncvs/src/sys/dev/pci/pcib_private.h,v retrieving revision 1.13 diff -u -r1.13 pcib_private.h --- pcib_private.h 30 Sep 2007 11:05:15 -0000 1.13 +++ pcib_private.h 21 Feb 2008 01:41:23 -0000 @@ -48,9 +48,10 @@ #define PCIB_SUBTRACTIVE 0x1 #define PCIB_DISABLE_MSI 0x2 uint16_t command; /* command register */ - uint32_t domain; /* domain number */ - uint8_t secbus; /* secondary bus number */ - uint8_t subbus; /* subordinate bus number */ + u_long domain; /* domain number */ + u_long secbus; /* secondary bus number */ + u_long subbus; /* subordinate bus number */ + u_long pribus; /* primary bus number */ pci_addr_t pmembase; /* base address of prefetchable memory */ pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ pci_addr_t membase; /* base address of memory window */
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