From owner-freebsd-arch@FreeBSD.ORG Sun May 22 08:19:42 2005 Return-Path: X-Original-To: freebsd-arch@freebsd.org Delivered-To: freebsd-arch@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 2C91916A41C; Sun, 22 May 2005 08:19:42 +0000 (GMT) (envelope-from marcel@xcllnt.net) Received: from ns1.xcllnt.net (209-128-86-226.bayarea.net [209.128.86.226]) by mx1.FreeBSD.org (Postfix) with ESMTP id A09DB43D48; Sun, 22 May 2005 08:19:41 +0000 (GMT) (envelope-from marcel@xcllnt.net) Received: from [192.168.4.250] (dhcp50.pn.xcllnt.net [192.168.4.250]) by ns1.xcllnt.net (8.13.3/8.13.3) with ESMTP id j4M8JfaJ024451; Sun, 22 May 2005 01:19:41 -0700 (PDT) (envelope-from marcel@xcllnt.net) In-Reply-To: <42900C01.10904@freebsd.org> References: <428FC00B.3080909@freebsd.org> <428FD710.4060200@freebsd.org> <9e8314b53980a379445cc8c07086901d@xcllnt.net> <428FE788.8020408@freebsd.org> <6451b639f2e0ddacb18f62c571dfeedb@xcllnt.net> <42900C01.10904@freebsd.org> Mime-Version: 1.0 (Apple Message framework v622) Content-Type: text/plain; charset=US-ASCII; format=flowed Message-Id: <401480a79de1cc474eec20c1943da574@xcllnt.net> Content-Transfer-Encoding: 7bit From: Marcel Moolenaar Date: Sun, 22 May 2005 01:19:40 -0700 To: Colin Percival X-Mailer: Apple Mail (2.622) Cc: freebsd-arch@freebsd.org Subject: Re: Scheduler fixes for hyperthreading X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 22 May 2005 08:19:42 -0000 On May 21, 2005, at 9:35 PM, Colin Percival wrote: > Marcel Moolenaar wrote: >> There are a lot of variables that need to be taken into account and >> those variables do not necessarily map perfectly from a P4 to an I2. >> Sharing of the L1 cache is not a sufficient condition to create a >> side-channel for timing attacks. A reliable time source with enough >> precision is also necessary (as you and Stephan have pointed out). >> The precision of the time source depends on latencies of the various >> cache levels and the micro-architectural behavior of the processor. > > Point taken. I maintain, however, that it is much better to make > "information can leak between these processors" a machine-independent > concept which is handled appropriately by the scheduler (with the > necessary machine-dependent code to specify *which* sets of processors, > if any, have such leakage). Yes, I agree. I forgot to explicitly acknowledge that point in my previous emails. Sorry about that... -- Marcel Moolenaar USPA: A-39004 marcel@xcllnt.net