Date: Sun, 2 Feb 1997 16:25:26 -0700 (MST) From: Terry Lambert <terry@lambert.org> To: smp@csn.net (Steve Passe) Cc: terry@lambert.org, davem@jenolan.rutgers.edu, michaelh@cet.co.jp, netdev@roxanne.nuclecu.unam.mx, roque@di.fc.ul.pt, freebsd-smp@FreeBSD.org, smpdev@roxanne.nuclecu.unam.mx Subject: Re: SMP Message-ID: <199702022325.QAA09083@phaeton.artisoft.com> In-Reply-To: <199702022232.PAA10876@clem.systemsix.com> from "Steve Passe" at Feb 2, 97 03:32:16 pm
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> i missed something here, could you clarify exactly what "this case" > means as reguards "seeing APIC_IO problems"? [ ... ] > > I don't know what lists you follow, but just in the past two days, > > the has been a person on the FreeBSD SMP list running a motherboard > > with "improved cache handling" that seems to be barfing on something > > like this when APIC_IO is used... 8-(. > > "improved cache handling" refers to a cache module that actually works, > ie tyan first shipped boards with a defective design, the fix for which > was a new, redesigned module. It is my belief that several people are > running tyan tomcat IIs with the APIC_IO option enabled. could > users confirm this for us? The guy with the "new, improved cache chips" can't run APIC_IO; it was on the SMP list... both yesterday and today, in fact. He has stated that compiling without the APIC_IO runs... > I have a theory about why this particular board is unhappy, but I need > further tests run before I can verify anything. But I don't think it > has anything to do with interaction of the APIC and cache coherency. OK... your theory is probably more likely correct than mine. What do you have to say about treating the cache line coherency? Is it necessary, or is it automatic? Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers.
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