From owner-freebsd-hackers@FreeBSD.ORG Fri Oct 10 20:03:23 2003 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id A5E5F16A4C0 for ; Fri, 10 Oct 2003 20:03:23 -0700 (PDT) Received: from c211-28-27-130.belrs2.nsw.optusnet.com.au (c211-28-27-130.belrs2.nsw.optusnet.com.au [211.28.27.130]) by mx1.FreeBSD.org (Postfix) with ESMTP id A6E3443F75 for ; Fri, 10 Oct 2003 20:03:19 -0700 (PDT) (envelope-from peterjeremy@optushome.com.au) Received: from server.c211-28-27-130.belrs2.nsw.optusnet.com.au (localhost.c211-28-27-130.belrs2.nsw.optusnet.com.au [127.0.0.1]) ESMTP id h9B32pdb076494; Sat, 11 Oct 2003 13:02:51 +1000 (EST) peter@server.c211-28-27-130.belrs2.nsw.optusnet.com.au) Received: (from peter@localhost) (8.12.9p1/8.12.9/Submit) id h9B32p2K076493; Sat, 11 Oct 2003 13:02:51 +1000 (EST) (envelope-from peter) Date: Sat, 11 Oct 2003 13:02:51 +1000 From: Peter Jeremy To: ticso@cicely.de Message-ID: <20031011030251.GB75796@server.c211-28-27-130.belrs2.nsw.optusnet.com.au> References: <20031008083059.GA520@garage.freebsd.pl> <20031008114506.I63940@beagle.fokus.fraunhofer.de> <20031009093741.GA69062@server.c211-28-27-130.belrs2.nsw.optusnet.com.au> <20031009172414.GY13791@cicely12.cicely.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20031009172414.GY13791@cicely12.cicely.de> User-Agent: Mutt/1.4.1i cc: freebsd-hackers@freebsd.org Subject: Re: Dynamic reads without locking. X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 11 Oct 2003 03:03:23 -0000 On Thu, Oct 09, 2003 at 07:24:15PM +0200, Bernd Walter wrote: >> Note that, possibly contrary to expectations, 8-bit and 16-bit >> _writes_ are not atomic on many (all?) the 64-bit architectures. >> Small writes are generally done by doing a 64-bit read, insert >> under mask and 64-bit write. > >The mask case is true - e.g. on alpha <=ev5, but it's still atomic. >You write the 8 or 16 bit in a single step, but the other bits of the >same 32bit memory location are loaded into a register as well and >masked. True. I think I expressed myself badly referring to it as "not atomic". >Note that this is semanticaly in no way different from a CPU loading >a whole cacheline to change a single byte which is what every modern >system does. Which may or may not provide hardware interlocking to support multiple CPUs updating adjacent memory. The load/mask/store situation definitely needs explicit interlocks. Maybe what I should say is that in a threaded or multi-CPU environment, updating any variable without locks requires intimate knowledge of how your toolchain lays out storage and what the system coherency boundaries are. To explain further, say I have two variables: short foo, bar; If the toolchain happens to pack them into the same longword on an Alpha and doesn't use the BWL-extension instructions then I can't update 'foo' in one thread and 'bar' in a different thread without locks. OTOH, if 'foo' and 'bar' are in different cache lines, then you don't need locks in any architecture. Peter