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Date: Tue, 14 May 1996 11:55:13 -0700
From: Sean Eric Fagan <sef@kithrup.com>
Message-Id: <199605141855.LAA00480@kithrup.com>
To: mmead@Glock.COM
Subject: Re: Triton chipset with 256k cache caches 32M only?
Newsgroups: kithrup.freebsd.hardware
In-Reply-To: <199605141313.JAA07905.kithrup.freebsd.hardware@Glock.COM>
References: <199605132318.BAA02422@uriah.heep.sax.de> from "J Wunsch" at May 14, 96 01:18:16 am
Organization: Kithrup Enterprises, Ltd.
Cc: hardware@freebsd.org
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In article <199605141313.JAA07905.kithrup.freebsd.hardware@Glock.COM> mead@Glock.COM writes:
>	I'd really like to do ECC, I just don't have the money for it right
>now.  So does this ECC work the same as the ECC on DEC Alphas?  On the Alphas,
>you put in 5M for every 4M of addressable ram.  Is there a fifth simm slot on
>these motherboards where a non ECC capable motherboard would have 4?

No, you use normal x36 SIMMs; for example, I bought two 4x36 60ns SIMMs for
my Triton-II motherboard (which has yet to arrive, admittedly ;)).

I'm assuming that, in ECC mode, the chipset always makes sure 64 bits are
fetched; with one bit of parity per 8-bit byte, that gives you 8 bits of
parity bits per 64-bit longword; that leaves a couple of extra bits more
than ECC requires.

Rod says that there is about a 10-15% performance penalty when using ECC
mode.  I'm looking around trying to see if I can get some programming
information on the chipset; it'd be nice if freebsd could actually *use* the
information, instead of just taking an NMI ;).

Sean.