From owner-svn-src-all@FreeBSD.ORG Mon Jan 12 21:58:19 2009 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id E80C61065679; Mon, 12 Jan 2009 21:58:19 +0000 (UTC) (envelope-from jkim@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id BB1A98FC12; Mon, 12 Jan 2009 21:58:19 +0000 (UTC) (envelope-from jkim@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n0CLwJ1B077434; Mon, 12 Jan 2009 21:58:19 GMT (envelope-from jkim@svn.freebsd.org) Received: (from jkim@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n0CLwJdG077433; Mon, 12 Jan 2009 21:58:19 GMT (envelope-from jkim@svn.freebsd.org) Message-Id: <200901122158.n0CLwJdG077433@svn.freebsd.org> From: Jung-uk Kim Date: Mon, 12 Jan 2009 21:58:19 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r187117 - head/sys/i386/i386 X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 12 Jan 2009 21:58:22 -0000 Author: jkim Date: Mon Jan 12 21:58:19 2009 New Revision: 187117 URL: http://svn.freebsd.org/changeset/base/187117 Log: Replace more strcmp(cpu_vendor, "foo") with cpu_vendor_id. Modified: head/sys/i386/i386/initcpu.c Modified: head/sys/i386/i386/initcpu.c ============================================================================== --- head/sys/i386/i386/initcpu.c Mon Jan 12 21:49:42 2009 (r187116) +++ head/sys/i386/i386/initcpu.c Mon Jan 12 21:58:19 2009 (r187117) @@ -650,7 +650,7 @@ initializecpu(void) init_6x86MX(); break; case CPU_686: - if (strcmp(cpu_vendor, "GenuineIntel") == 0) { + if (cpu_vendor_id == CPU_VENDOR_INTEL) { switch (cpu_id & 0xff0) { case 0x610: init_ppro(); @@ -659,7 +659,7 @@ initializecpu(void) init_mendocino(); break; } - } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { + } else if (cpu_vendor_id == CPU_VENDOR_AMD) { #if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK) /* * Sometimes the BIOS doesn't enable SSE instructions. @@ -678,7 +678,7 @@ initializecpu(void) cpu_feature = regs[3]; } #endif - } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) { + } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) { switch (cpu_id & 0xff0) { case 0x690: if ((cpu_id & 0xf) < 3) @@ -718,7 +718,7 @@ initializecpu(void) * CPU_UPGRADE_HW_CACHE option in your kernel configuration file. * This option eliminates unneeded cache flush instruction(s). */ - if (strcmp(cpu_vendor, "CyrixInstead") == 0) { + if (cpu_vendor_id == CPU_VENDOR_CYRIX) { switch (cpu) { #ifdef I486_CPU case CPU_486DLC: @@ -737,7 +737,7 @@ initializecpu(void) default: break; } - } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { + } else if (cpu_vendor_id == CPU_VENDOR_AMD) { switch (cpu_id & 0xFF0) { case 0x470: /* Enhanced Am486DX2 WB */ case 0x490: /* Enhanced Am486DX4 WB */ @@ -745,7 +745,7 @@ initializecpu(void) need_pre_dma_flush = 1; break; } - } else if (strcmp(cpu_vendor, "IBM") == 0) { + } else if (cpu_vendor_id == CPU_VENDOR_IBM) { need_post_dma_flush = 1; } else { #ifdef CPU_I486_ON_386 @@ -941,7 +941,7 @@ DB_SHOW_COMMAND(cyrixreg, cyrixreg) u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0; cr0 = rcr0(); - if (strcmp(cpu_vendor,"CyrixInstead") == 0) { + if (cpu_vendor_id == CPU_VENDOR_CYRIX) { eflags = read_eflags(); disable_intr();