From owner-freebsd-current Thu Feb 8 18: 8:22 2001 Delivered-To: freebsd-current@freebsd.org Received: from mail.du.gtn.com (mail.du.gtn.com [194.77.9.57]) by hub.freebsd.org (Postfix) with ESMTP id 1B3DF37B69C for ; Thu, 8 Feb 2001 18:08:02 -0800 (PST) Received: from mail.cicely.de (cicely.de [194.231.9.142]) by mail.du.gtn.com (8.11.0.Beta3/8.11.0.Beta3) with ESMTP id f1927xS09810 (using TLSv1/SSLv3 with cipher EDH-RSA-DES-CBC3-SHA (168 bits) verified OK) for ; Fri, 9 Feb 2001 03:08:00 +0100 (MET) Received: from cicely5.cicely.de (cicely5.cicely.de [fec0:0:0:104::5]) by mail.cicely.de (8.11.0.Beta1/8.11.0.Beta1) with ESMTP id f1928JP81298 (using TLSv1/SSLv3 with cipher EDH-RSA-DES-CBC3-SHA (168 bits) verified NO) for ; Fri, 9 Feb 2001 03:08:27 +0100 (CET) Received: (from ticso@localhost) by cicely5.cicely.de (8.11.1/8.11.1) id f1928Jl82131 for freebsd-current@FreeBSD.ORG; Fri, 9 Feb 2001 03:08:19 +0100 (CET) (envelope-from ticso) Date: Fri, 9 Feb 2001 03:08:19 +0100 From: Bernd Walter To: freebsd-current@FreeBSD.ORG Subject: Re: atomic_ question Message-ID: <20010209030819.C81461@cicely5.cicely.de> References: <20010208182106.B80741@cicely5.cicely.de> <20010209075749.Z90937@gsmx07.alcatel.com.au> <20010208222131.D81067@cicely5.cicely.de> <20010209110004.D90937@gsmx07.alcatel.com.au> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Mailer: Mutt 1.0.1i In-Reply-To: <20010209110004.D90937@gsmx07.alcatel.com.au>; from peter.jeremy@alcatel.com.au on Fri, Feb 09, 2001 at 11:00:04AM +1100 Sender: owner-freebsd-current@FreeBSD.ORG Precedence: bulk X-Loop: FreeBSD.ORG On Fri, Feb 09, 2001 at 11:00:04AM +1100, Peter Jeremy wrote: > On 2001-Feb-08 22:21:32 +0100, Bernd Walter wrote: > >On sparcv8 you don't have an operation doing conditionaly stores and > >you don't have RMW operations. > >The only way to do is to have a global lock variable on which you spin > >until the current client finishes. > > The SPARC architecture supports SMP so there must be some > synchronisation primitive that works between processors (disabling > interrupts only works on the current processor). Normally the same > primitive can be used to synchronise accesses within the same > processor. I know the older SPARC's had a test-and-set instruction > which was locked RMW - there must be something similar in v8 and v9. sparcv8 has: LDSTUB - which is a atomic load into register and store 0xff SWAP - which exchanges a register with memory atomicly sparcv9 has additionaly the Comapare And Set (CAS) operation which makes it similar in use as alpha. I can't speak for sparcv7 and older but maybe you are refering to sparcv9 with it's CAS operation as an "older" SPARC or have a vendor specific extension in mind. Disabling interrupts will work fine because the reason is to avoid deadlocks. The only thing needed is that the processor holding the lock can't be interrupted until it's finished. If another CPU want's the same lock it can spinwait because the other CPU still gets the chance to release the lock. No doubt the available primitives are enough - but I wanted to know if its neccessary to go the complete ugly way. The sparv8 way for FreeBSDs atomic_ is now clear to me: disable ints for the CPU in question fetch the lock do the real work wmb unlock restore ints Thank you all for making this clear. -- B.Walter COSMO-Project http://www.cosmo-project.de ticso@cicely.de Usergroup info@cosmo-project.de To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-current" in the body of the message