From owner-freebsd-arch Wed Aug 22 9:41: 5 2001 Delivered-To: freebsd-arch@freebsd.org Received: from tasogare.imasy.or.jp (tasogare.imasy.or.jp [202.227.24.5]) by hub.freebsd.org (Postfix) with ESMTP id E164D37B41A; Wed, 22 Aug 2001 09:40:49 -0700 (PDT) (envelope-from iwasaki@jp.FreeBSD.org) Received: from localhost (iwasaki.imasy.or.jp [202.227.24.92]) by tasogare.imasy.or.jp (8.11.3+3.4W/8.11.3/tasogare/smtpfeed 1.12) with ESMTP/inet id f7MGeRI50789; Thu, 23 Aug 2001 01:40:27 +0900 (JST) (envelope-from iwasaki@jp.FreeBSD.org) To: tlambert2@mindspring.com Cc: peter@wemm.org, iwasaki@jp.FreeBSD.org, arch@FreeBSD.ORG, audit@FreeBSD.ORG, kumabu@t3.rim.or.jp Subject: Re: CFR: Timing to enable CR4.PGE bit In-Reply-To: <3B837418.2D5529E5@mindspring.com> References: <20010822082749.ED86038FD@overcee.netplex.com.au> <3B837418.2D5529E5@mindspring.com> X-Mailer: Mew version 1.94.1 on Emacs 19.34 / Mule 2.3 (SUETSUMUHANA) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-Id: <20010823014025T.iwasaki@jp.FreeBSD.org> Date: Thu, 23 Aug 2001 01:40:25 +0900 From: Mitsuru IWASAKI X-Dispatcher: imput version 20000228(IM140) Lines: 35 Sender: owner-freebsd-arch@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.ORG Hi, thanks folks for comments and sorry for my late reply. Terry Lambert wrote: > Peter Wemm wrote: > > Page Global Enable (bit 7 of CR4). (Introduced in the P6 family > > processors.) Enables the global page feature when set; disables the > > global page feature when clear. [snip] In addition, the bit must not > > ^^^^^^^^^^^^^^^^ > > be enabled before paging is enabled via CR0.PG. Program correctness > > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > > may be affected by reversing this sequence, and processor performance > > will be impacted. > > ---- > > > > Currently, we enable CR4.PGE bit in create_pagetables, then enable > > CR0.PG in locore.s. This seems to violate Intel's note. > > Ah. It looked like an inverted patch to me... it moved the > code from line 725 or so in locore.s to line 375. I've just committed only part of moving CR4.PGE enabling code after paging is enabled. It was my primary goal to avoid violating the rules in the CPU developer's manual. Thanks folks! Another part of my original post was just for my curiosity, it's not so important. I thought it would be valuable to be considered if we can get better performance by moving CR4.PGE bit on to later stage without a lot of efforts. But I'm not sure how effective it is. There may be hardly effect. Does anyone test and measure it under suitable environment? If we get good result by this without any problems, then we can consider this issue again (including how to fire PGE enabling code as Bruce suggested), I think. Thanks To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-arch" in the body of the message