Date: Mon, 11 Jan 2021 15:36:05 GMT From: Roger Pau Monné <royger@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 5ed9deef6b1e - main - xen: update interface headers Message-ID: <202101111536.10BFa5qf026579@gitrepo.freebsd.org>
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The branch main has been updated by royger: URL: https://cgit.FreeBSD.org/src/commit/?id=5ed9deef6b1e781931dc0195e4f9924a2d1ee189 commit 5ed9deef6b1e781931dc0195e4f9924a2d1ee189 Author: Roger Pau Monné <royger@FreeBSD.org> AuthorDate: 2020-12-30 11:31:12 +0000 Commit: Roger Pau Monné <royger@FreeBSD.org> CommitDate: 2021-01-11 15:14:59 +0000 xen: update interface headers This is a verbatim copy of the public headers from Xen 4.14.1. No functional change intended. Sponsored by: Citrix Systems R&D --- sys/xen/interface/arch-arm.h | 92 +- sys/xen/interface/arch-arm/smccc.h | 66 ++ sys/xen/interface/arch-x86/cpufeatureset.h | 295 ++++++ sys/xen/interface/arch-x86/cpuid.h | 42 +- sys/xen/interface/arch-x86/hvm/.save.h.swp | Bin 0 -> 16384 bytes sys/xen/interface/arch-x86/hvm/save.h | 148 +-- sys/xen/interface/arch-x86/pmu.h | 13 +- sys/xen/interface/arch-x86/xen-mca.h | 73 +- sys/xen/interface/arch-x86/xen-x86_32.h | 70 +- sys/xen/interface/arch-x86/xen-x86_64.h | 101 +- sys/xen/interface/arch-x86/xen.h | 96 +- sys/xen/interface/arch-x86_32.h | 4 +- sys/xen/interface/arch-x86_64.h | 4 +- sys/xen/interface/argo.h | 255 ++++++ sys/xen/interface/device_tree_defs.h | 42 + sys/xen/interface/dom0_ops.h | 4 +- sys/xen/interface/domctl.h | 521 ++++++----- sys/xen/interface/elfnote.h | 9 +- sys/xen/interface/errno.h | 54 +- sys/xen/interface/event_channel.h | 7 +- sys/xen/interface/features.h | 16 +- sys/xen/interface/grant_table.h | 24 +- sys/xen/interface/hvm/dm_op.h | 480 ++++++++++ sys/xen/interface/hvm/e820.h | 5 +- sys/xen/interface/hvm/hvm_info_table.h | 10 +- sys/xen/interface/hvm/hvm_op.h | 359 +++----- sys/xen/interface/hvm/hvm_vcpu.h | 144 +++ sys/xen/interface/hvm/hvm_xs_strings.h | 7 + sys/xen/interface/hvm/ioreq.h | 18 +- sys/xen/interface/hvm/params.h | 164 +++- sys/xen/interface/hvm/pvdrivers.h | 6 +- sys/xen/interface/hvm/save.h | 45 +- sys/xen/interface/hypfs.h | 129 +++ sys/xen/interface/io/9pfs.h | 49 + sys/xen/interface/io/blkif.h | 112 ++- sys/xen/interface/io/cameraif.h | 1374 ++++++++++++++++++++++++++++ sys/xen/interface/io/console.h | 9 +- sys/xen/interface/io/displif.h | 872 ++++++++++++++++++ sys/xen/interface/io/fsif.h | 8 +- sys/xen/interface/io/kbdif.h | 498 +++++++++- sys/xen/interface/io/libxenvchan.h | 1 + sys/xen/interface/io/netif.h | 801 ++++++++++++++-- sys/xen/interface/io/protocols.h | 2 +- sys/xen/interface/io/pvcalls.h | 160 ++++ sys/xen/interface/io/ring.h | 222 ++++- sys/xen/interface/io/sndif.h | 1091 ++++++++++++++++++++++ sys/xen/interface/io/tpmif.h | 1 + sys/xen/interface/io/usbif.h | 6 +- sys/xen/interface/io/vscsiif.h | 77 +- sys/xen/interface/io/xs_wire.h | 10 +- sys/xen/interface/kexec.h | 28 +- sys/xen/interface/memory.h | 161 +++- sys/xen/interface/nmi.h | 4 +- sys/xen/interface/physdev.h | 10 +- sys/xen/interface/platform.h | 10 +- sys/xen/interface/pmu.h | 14 +- sys/xen/interface/sched.h | 29 +- sys/xen/interface/sysctl.h | 604 +++++++++--- sys/xen/interface/tmem.h | 22 +- sys/xen/interface/trace.h | 12 +- sys/xen/interface/vcpu.h | 26 +- sys/xen/interface/version.h | 25 +- sys/xen/interface/vm_event.h | 196 +++- sys/xen/interface/xen-compat.h | 15 +- sys/xen/interface/xen.h | 223 +++-- sys/xen/interface/xenoprof.h | 6 +- sys/xen/interface/xsm/flask_op.h | 6 +- 67 files changed, 8785 insertions(+), 1202 deletions(-) diff --git a/sys/xen/interface/arch-arm.h b/sys/xen/interface/arch-arm.h index 9a96401878f5..c365b1b39eaa 100644 --- a/sys/xen/interface/arch-arm.h +++ b/sys/xen/interface/arch-arm.h @@ -61,15 +61,15 @@ * * All memory which is shared with other entities in the system * (including the hypervisor and other guests) must reside in memory - * which is mapped as Normal Inner-cacheable. This applies to: + * which is mapped as Normal Inner Write-Back Outer Write-Back Inner-Shareable. + * This applies to: * - hypercall arguments passed via a pointer to guest memory. * - memory shared via the grant table mechanism (including PV I/O * rings etc). * - memory shared with the hypervisor (struct shared_info, struct * vcpu_info, the grant table, etc). * - * Any Inner cache allocation strategy (Write-Back, Write-Through etc) - * is acceptable. There is no restriction on the Outer-cacheability. + * Any cache allocation hints are acceptable. */ /* @@ -173,7 +173,7 @@ typedef union { type *p; unsigned long q; } \ __guest_handle_ ## name; \ typedef union { type *p; uint64_aligned_t q; } \ - __guest_handle_64_ ## name; + __guest_handle_64_ ## name /* * XEN_GUEST_HANDLE represents a guest pointer, when passed as a field @@ -195,11 +195,22 @@ _sxghr_tmp->q = 0; \ _sxghr_tmp->p = val; \ } while ( 0 ) -#ifdef __XEN_TOOLS__ -#define get_xen_guest_handle(val, hnd) do { val = (hnd).p; } while (0) -#endif #define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val) +typedef uint64_t xen_pfn_t; +#define PRI_xen_pfn PRIx64 +#define PRIu_xen_pfn PRIu64 + +/* + * Maximum number of virtual CPUs in legacy multi-processor guests. + * Only one. All other VCPUS must use VCPUOP_register_vcpu_info. + */ +#define XEN_LEGACY_MAX_VCPUS 1 + +typedef uint64_t xen_ulong_t; +#define PRI_xen_ulong PRIx64 + +#if defined(__XEN__) || defined(__XEN_TOOLS__) #if defined(__GNUC__) && !defined(__STRICT_ANSI__) /* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */ # define __DECL_REG(n64, n32) union { \ @@ -275,17 +286,6 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_core_regs_t); #undef __DECL_REG -typedef uint64_t xen_pfn_t; -#define PRI_xen_pfn PRIx64 - -/* Maximum number of virtual CPUs in legacy multi-processor guests. */ -/* Only one. All other VCPUS must use VCPUOP_register_vcpu_info */ -#define XEN_LEGACY_MAX_VCPUS 1 - -typedef uint64_t xen_ulong_t; -#define PRI_xen_ulong PRIx64 - -#if defined(__XEN__) || defined(__XEN_TOOLS__) struct vcpu_guest_context { #define _VGCF_online 0 #define VGCF_online (1<<_VGCF_online) @@ -293,7 +293,7 @@ struct vcpu_guest_context { struct vcpu_guest_core_regs user_regs; /* Core CPU registers */ - uint32_t sctlr; + uint64_t sctlr; uint64_t ttbcr, ttbr0, ttbr1; }; typedef struct vcpu_guest_context vcpu_guest_context_t; @@ -306,10 +306,16 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); #define XEN_DOMCTL_CONFIG_GIC_NATIVE 0 #define XEN_DOMCTL_CONFIG_GIC_V2 1 #define XEN_DOMCTL_CONFIG_GIC_V3 2 + +#define XEN_DOMCTL_CONFIG_TEE_NONE 0 +#define XEN_DOMCTL_CONFIG_TEE_OPTEE 1 + struct xen_arch_domainconfig { /* IN/OUT */ uint8_t gic_version; /* IN */ + uint16_t tee_type; + /* IN */ uint32_t nr_spis; /* * OUT @@ -376,7 +382,7 @@ typedef uint64_t xen_callback_t; #define PSR_GUEST32_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_SVC) #define PSR_GUEST64_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_EL1h) -#define SCTLR_GUEST_INIT 0x00c50078 +#define SCTLR_GUEST_INIT xen_mk_ullong(0x00c50078) /* * Virtual machine platform (memory layout, interrupts) @@ -394,38 +400,45 @@ typedef uint64_t xen_callback_t; */ /* vGIC v2 mappings */ -#define GUEST_GICD_BASE 0x03001000ULL -#define GUEST_GICD_SIZE 0x00001000ULL -#define GUEST_GICC_BASE 0x03002000ULL -#define GUEST_GICC_SIZE 0x00000100ULL +#define GUEST_GICD_BASE xen_mk_ullong(0x03001000) +#define GUEST_GICD_SIZE xen_mk_ullong(0x00001000) +#define GUEST_GICC_BASE xen_mk_ullong(0x03002000) +#define GUEST_GICC_SIZE xen_mk_ullong(0x00002000) /* vGIC v3 mappings */ -#define GUEST_GICV3_GICD_BASE 0x03001000ULL -#define GUEST_GICV3_GICD_SIZE 0x00010000ULL +#define GUEST_GICV3_GICD_BASE xen_mk_ullong(0x03001000) +#define GUEST_GICV3_GICD_SIZE xen_mk_ullong(0x00010000) -#define GUEST_GICV3_RDIST_STRIDE 0x20000ULL #define GUEST_GICV3_RDIST_REGIONS 1 -#define GUEST_GICV3_GICR0_BASE 0x03020000ULL /* vCPU0 - vCPU127 */ -#define GUEST_GICV3_GICR0_SIZE 0x01000000ULL +#define GUEST_GICV3_GICR0_BASE xen_mk_ullong(0x03020000) /* vCPU0..127 */ +#define GUEST_GICV3_GICR0_SIZE xen_mk_ullong(0x01000000) + +/* ACPI tables physical address */ +#define GUEST_ACPI_BASE xen_mk_ullong(0x20000000) +#define GUEST_ACPI_SIZE xen_mk_ullong(0x02000000) + +/* PL011 mappings */ +#define GUEST_PL011_BASE xen_mk_ullong(0x22000000) +#define GUEST_PL011_SIZE xen_mk_ullong(0x00001000) /* * 16MB == 4096 pages reserved for guest to use as a region to map its * grant table in. */ -#define GUEST_GNTTAB_BASE 0x38000000ULL -#define GUEST_GNTTAB_SIZE 0x01000000ULL +#define GUEST_GNTTAB_BASE xen_mk_ullong(0x38000000) +#define GUEST_GNTTAB_SIZE xen_mk_ullong(0x01000000) -#define GUEST_MAGIC_BASE 0x39000000ULL -#define GUEST_MAGIC_SIZE 0x01000000ULL +#define GUEST_MAGIC_BASE xen_mk_ullong(0x39000000) +#define GUEST_MAGIC_SIZE xen_mk_ullong(0x01000000) #define GUEST_RAM_BANKS 2 -#define GUEST_RAM0_BASE 0x40000000ULL /* 3GB of low RAM @ 1GB */ -#define GUEST_RAM0_SIZE 0xc0000000ULL +#define GUEST_RAM0_BASE xen_mk_ullong(0x40000000) /* 3GB of low RAM @ 1GB */ +#define GUEST_RAM0_SIZE xen_mk_ullong(0xc0000000) -#define GUEST_RAM1_BASE 0x0200000000ULL /* 1016GB of RAM @ 8GB */ -#define GUEST_RAM1_SIZE 0xfe00000000ULL +#define GUEST_RAM1_BASE xen_mk_ullong(0x0200000000) /* 1016GB of RAM @ 8GB */ +#define GUEST_RAM1_SIZE xen_mk_ullong(0xfe00000000) #define GUEST_RAM_BASE GUEST_RAM0_BASE /* Lowest RAM address */ /* Largest amount of actual RAM, not including holes */ @@ -434,12 +447,17 @@ typedef uint64_t xen_callback_t; #define GUEST_RAM_BANK_BASES { GUEST_RAM0_BASE, GUEST_RAM1_BASE } #define GUEST_RAM_BANK_SIZES { GUEST_RAM0_SIZE, GUEST_RAM1_SIZE } +/* Current supported guest VCPUs */ +#define GUEST_MAX_VCPUS 128 + /* Interrupts */ #define GUEST_TIMER_VIRT_PPI 27 #define GUEST_TIMER_PHYS_S_PPI 29 #define GUEST_TIMER_PHYS_NS_PPI 30 #define GUEST_EVTCHN_PPI 31 +#define GUEST_VPL011_SPI 32 + /* PSCI functions */ #define PSCI_cpu_suspend 0 #define PSCI_cpu_off 1 diff --git a/sys/xen/interface/arch-arm/smccc.h b/sys/xen/interface/arch-arm/smccc.h new file mode 100644 index 000000000000..17dc6d8829e6 --- /dev/null +++ b/sys/xen/interface/arch-arm/smccc.h @@ -0,0 +1,66 @@ +/* + * smccc.h + * + * SMC/HVC interface in accordance with SMC Calling Convention. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Copyright 2017 (C) EPAM Systems + */ + +#ifndef __XEN_PUBLIC_ARCH_ARM_SMCCC_H__ +#define __XEN_PUBLIC_ARCH_ARM_SMCCC_H__ + +#include "public/xen.h" + +/* + * Hypervisor Service version. + * + * We can't use XEN version here, because of SMCCC requirements: + * Major revision should change every time SMC/HVC function is removed. + * Minor revision should change every time SMC/HVC function is added. + * So, it is SMCCC protocol revision code, not XEN version. + * + * Those values are subjected to change, when interface will be extended. + */ +#define XEN_SMCCC_MAJOR_REVISION 0 +#define XEN_SMCCC_MINOR_REVISION 1 + +/* Hypervisor Service UID. Randomly generated with uuidgen. */ +#define XEN_SMCCC_UID XEN_DEFINE_UUID(0xa71812dc, 0xc698, 0x4369, 0x9acf, \ + 0x79, 0xd1, 0x8d, 0xde, 0xe6, 0x67) + +/* Standard Service Service Call version. */ +#define SSSC_SMCCC_MAJOR_REVISION 0 +#define SSSC_SMCCC_MINOR_REVISION 1 + +/* Standard Service Call UID. Randomly generated with uuidgen. */ +#define SSSC_SMCCC_UID XEN_DEFINE_UUID(0xf863386f, 0x4b39, 0x4cbd, 0x9220,\ + 0xce, 0x16, 0x41, 0xe5, 0x9f, 0x6f) + +#endif /* __XEN_PUBLIC_ARCH_ARM_SMCCC_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End:b + */ diff --git a/sys/xen/interface/arch-x86/cpufeatureset.h b/sys/xen/interface/arch-x86/cpufeatureset.h new file mode 100644 index 000000000000..d06a2fd4c8e2 --- /dev/null +++ b/sys/xen/interface/arch-x86/cpufeatureset.h @@ -0,0 +1,295 @@ +/* + * arch-x86/cpufeatureset.h + * + * CPU featureset definitions + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Copyright (c) 2015, 2016 Citrix Systems, Inc. + */ + +/* + * There are two expected ways of including this header. + * + * 1) The "default" case (expected from tools etc). + * + * Simply #include <public/arch-x86/cpufeatureset.h> + * + * In this circumstance, normal header guards apply and the includer shall get + * an enumeration in the XEN_X86_FEATURE_xxx namespace. + * + * 2) The special case where the includer provides XEN_CPUFEATURE() in scope. + * + * In this case, no inclusion guards apply and the caller is responsible for + * their XEN_CPUFEATURE() being appropriate in the included context. + */ + +#ifndef XEN_CPUFEATURE + +/* + * Includer has not provided a custom XEN_CPUFEATURE(). Arrange for normal + * header guards, an enum and constants in the XEN_X86_FEATURE_xxx namespace. + */ +#ifndef __XEN_PUBLIC_ARCH_X86_CPUFEATURESET_H__ +#define __XEN_PUBLIC_ARCH_X86_CPUFEATURESET_H__ + +#define XEN_CPUFEATURESET_DEFAULT_INCLUDE + +#define XEN_CPUFEATURE(name, value) XEN_X86_FEATURE_##name = value, +enum { + +#endif /* __XEN_PUBLIC_ARCH_X86_CPUFEATURESET_H__ */ +#endif /* !XEN_CPUFEATURE */ + + +#ifdef XEN_CPUFEATURE +/* + * A featureset is a bitmap of x86 features, represented as a collection of + * 32bit words. + * + * Words are as specified in vendors programming manuals, and shall not + * contain any synthesied values. New words may be added to the end of + * featureset. + * + * All featureset words currently originate from leaves specified for the + * CPUID instruction, but this is not preclude other sources of information. + */ + +/* + * Attribute syntax: + * + * Attributes for a particular feature are provided as characters before the + * first space in the comment immediately following the feature value. Note - + * none of these attributes form part of the Xen public ABI. + * + * Special: '!' + * This bit has special properties and is not a straight indication of a + * piece of new functionality. Xen will handle these differently, + * and may override toolstack settings completely. + * + * Applicability to guests: 'A', 'S' or 'H' + * 'A' = All guests. + * 'S' = All HVM guests (not PV guests). + * 'H' = HVM HAP guests (not PV or HVM Shadow guests). + * Upper case => Available by default + * Lower case => Can be opted-in to, but not available by default. + */ + +/* Intel-defined CPU features, CPUID level 0x00000001.edx, word 0 */ +XEN_CPUFEATURE(FPU, 0*32+ 0) /*A Onboard FPU */ +XEN_CPUFEATURE(VME, 0*32+ 1) /*S Virtual Mode Extensions */ +XEN_CPUFEATURE(DE, 0*32+ 2) /*A Debugging Extensions */ +XEN_CPUFEATURE(PSE, 0*32+ 3) /*S Page Size Extensions */ +XEN_CPUFEATURE(TSC, 0*32+ 4) /*A Time Stamp Counter */ +XEN_CPUFEATURE(MSR, 0*32+ 5) /*A Model-Specific Registers, RDMSR, WRMSR */ +XEN_CPUFEATURE(PAE, 0*32+ 6) /*A Physical Address Extensions */ +XEN_CPUFEATURE(MCE, 0*32+ 7) /*A Machine Check Architecture */ +XEN_CPUFEATURE(CX8, 0*32+ 8) /*A CMPXCHG8 instruction */ +XEN_CPUFEATURE(APIC, 0*32+ 9) /*!A Onboard APIC */ +XEN_CPUFEATURE(SEP, 0*32+11) /*A SYSENTER/SYSEXIT */ +XEN_CPUFEATURE(MTRR, 0*32+12) /*S Memory Type Range Registers */ +XEN_CPUFEATURE(PGE, 0*32+13) /*S Page Global Enable */ +XEN_CPUFEATURE(MCA, 0*32+14) /*A Machine Check Architecture */ +XEN_CPUFEATURE(CMOV, 0*32+15) /*A CMOV instruction (FCMOVCC and FCOMI too if FPU present) */ +XEN_CPUFEATURE(PAT, 0*32+16) /*A Page Attribute Table */ +XEN_CPUFEATURE(PSE36, 0*32+17) /*S 36-bit PSEs */ +XEN_CPUFEATURE(CLFLUSH, 0*32+19) /*A CLFLUSH instruction */ +XEN_CPUFEATURE(DS, 0*32+21) /* Debug Store */ +XEN_CPUFEATURE(ACPI, 0*32+22) /*A ACPI via MSR */ +XEN_CPUFEATURE(MMX, 0*32+23) /*A Multimedia Extensions */ +XEN_CPUFEATURE(FXSR, 0*32+24) /*A FXSAVE and FXRSTOR instructions */ +XEN_CPUFEATURE(SSE, 0*32+25) /*A Streaming SIMD Extensions */ +XEN_CPUFEATURE(SSE2, 0*32+26) /*A Streaming SIMD Extensions-2 */ +XEN_CPUFEATURE(SS, 0*32+27) /*A CPU self snoop */ +XEN_CPUFEATURE(HTT, 0*32+28) /*!A Hyper-Threading Technology */ +XEN_CPUFEATURE(TM1, 0*32+29) /* Thermal Monitor 1 */ +XEN_CPUFEATURE(PBE, 0*32+31) /* Pending Break Enable */ + +/* Intel-defined CPU features, CPUID level 0x00000001.ecx, word 1 */ +XEN_CPUFEATURE(SSE3, 1*32+ 0) /*A Streaming SIMD Extensions-3 */ +XEN_CPUFEATURE(PCLMULQDQ, 1*32+ 1) /*A Carry-less multiplication */ +XEN_CPUFEATURE(DTES64, 1*32+ 2) /* 64-bit Debug Store */ +XEN_CPUFEATURE(MONITOR, 1*32+ 3) /* Monitor/Mwait support */ +XEN_CPUFEATURE(DSCPL, 1*32+ 4) /* CPL Qualified Debug Store */ +XEN_CPUFEATURE(VMX, 1*32+ 5) /*S Virtual Machine Extensions */ +XEN_CPUFEATURE(SMX, 1*32+ 6) /* Safer Mode Extensions */ +XEN_CPUFEATURE(EIST, 1*32+ 7) /* Enhanced SpeedStep */ +XEN_CPUFEATURE(TM2, 1*32+ 8) /* Thermal Monitor 2 */ +XEN_CPUFEATURE(SSSE3, 1*32+ 9) /*A Supplemental Streaming SIMD Extensions-3 */ +XEN_CPUFEATURE(FMA, 1*32+12) /*A Fused Multiply Add */ +XEN_CPUFEATURE(CX16, 1*32+13) /*A CMPXCHG16B */ +XEN_CPUFEATURE(XTPR, 1*32+14) /* Send Task Priority Messages */ +XEN_CPUFEATURE(PDCM, 1*32+15) /* Perf/Debug Capability MSR */ +XEN_CPUFEATURE(PCID, 1*32+17) /*H Process Context ID */ +XEN_CPUFEATURE(DCA, 1*32+18) /* Direct Cache Access */ +XEN_CPUFEATURE(SSE4_1, 1*32+19) /*A Streaming SIMD Extensions 4.1 */ +XEN_CPUFEATURE(SSE4_2, 1*32+20) /*A Streaming SIMD Extensions 4.2 */ +XEN_CPUFEATURE(X2APIC, 1*32+21) /*!A Extended xAPIC */ +XEN_CPUFEATURE(MOVBE, 1*32+22) /*A movbe instruction */ +XEN_CPUFEATURE(POPCNT, 1*32+23) /*A POPCNT instruction */ +XEN_CPUFEATURE(TSC_DEADLINE, 1*32+24) /*S TSC Deadline Timer */ +XEN_CPUFEATURE(AESNI, 1*32+25) /*A AES instructions */ +XEN_CPUFEATURE(XSAVE, 1*32+26) /*A XSAVE/XRSTOR/XSETBV/XGETBV */ +XEN_CPUFEATURE(OSXSAVE, 1*32+27) /*! OSXSAVE */ +XEN_CPUFEATURE(AVX, 1*32+28) /*A Advanced Vector Extensions */ +XEN_CPUFEATURE(F16C, 1*32+29) /*A Half-precision convert instruction */ +XEN_CPUFEATURE(RDRAND, 1*32+30) /*!A Digital Random Number Generator */ +XEN_CPUFEATURE(HYPERVISOR, 1*32+31) /*!A Running under some hypervisor */ + +/* AMD-defined CPU features, CPUID level 0x80000001.edx, word 2 */ +XEN_CPUFEATURE(SYSCALL, 2*32+11) /*A SYSCALL/SYSRET */ +XEN_CPUFEATURE(NX, 2*32+20) /*A Execute Disable */ +XEN_CPUFEATURE(MMXEXT, 2*32+22) /*A AMD MMX extensions */ +XEN_CPUFEATURE(FFXSR, 2*32+25) /*A FFXSR instruction optimizations */ +XEN_CPUFEATURE(PAGE1GB, 2*32+26) /*H 1Gb large page support */ +XEN_CPUFEATURE(RDTSCP, 2*32+27) /*A RDTSCP */ +XEN_CPUFEATURE(LM, 2*32+29) /*A Long Mode (x86-64) */ +XEN_CPUFEATURE(3DNOWEXT, 2*32+30) /*A AMD 3DNow! extensions */ +XEN_CPUFEATURE(3DNOW, 2*32+31) /*A 3DNow! */ + +/* AMD-defined CPU features, CPUID level 0x80000001.ecx, word 3 */ +XEN_CPUFEATURE(LAHF_LM, 3*32+ 0) /*A LAHF/SAHF in long mode */ +XEN_CPUFEATURE(CMP_LEGACY, 3*32+ 1) /*!A If yes HyperThreading not valid */ +XEN_CPUFEATURE(SVM, 3*32+ 2) /*S Secure virtual machine */ +XEN_CPUFEATURE(EXTAPIC, 3*32+ 3) /* Extended APIC space */ +XEN_CPUFEATURE(CR8_LEGACY, 3*32+ 4) /*S CR8 in 32-bit mode */ +XEN_CPUFEATURE(ABM, 3*32+ 5) /*A Advanced bit manipulation */ +XEN_CPUFEATURE(SSE4A, 3*32+ 6) /*A SSE-4A */ +XEN_CPUFEATURE(MISALIGNSSE, 3*32+ 7) /*A Misaligned SSE mode */ +XEN_CPUFEATURE(3DNOWPREFETCH, 3*32+ 8) /*A 3DNow prefetch instructions */ +XEN_CPUFEATURE(OSVW, 3*32+ 9) /* OS Visible Workaround */ +XEN_CPUFEATURE(IBS, 3*32+10) /* Instruction Based Sampling */ +XEN_CPUFEATURE(XOP, 3*32+11) /*A extended AVX instructions */ +XEN_CPUFEATURE(SKINIT, 3*32+12) /* SKINIT/STGI instructions */ +XEN_CPUFEATURE(WDT, 3*32+13) /* Watchdog timer */ +XEN_CPUFEATURE(LWP, 3*32+15) /* Light Weight Profiling */ +XEN_CPUFEATURE(FMA4, 3*32+16) /*A 4 operands MAC instructions */ +XEN_CPUFEATURE(NODEID_MSR, 3*32+19) /* NodeId MSR */ +XEN_CPUFEATURE(TBM, 3*32+21) /*A trailing bit manipulations */ +XEN_CPUFEATURE(TOPOEXT, 3*32+22) /* topology extensions CPUID leafs */ +XEN_CPUFEATURE(DBEXT, 3*32+26) /*A data breakpoint extension */ +XEN_CPUFEATURE(MONITORX, 3*32+29) /* MONITOR extension (MONITORX/MWAITX) */ + +/* Intel-defined CPU features, CPUID level 0x0000000D:1.eax, word 4 */ +XEN_CPUFEATURE(XSAVEOPT, 4*32+ 0) /*A XSAVEOPT instruction */ +XEN_CPUFEATURE(XSAVEC, 4*32+ 1) /*A XSAVEC/XRSTORC instructions */ +XEN_CPUFEATURE(XGETBV1, 4*32+ 2) /*A XGETBV with %ecx=1 */ +XEN_CPUFEATURE(XSAVES, 4*32+ 3) /*S XSAVES/XRSTORS instructions */ + +/* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */ +XEN_CPUFEATURE(FSGSBASE, 5*32+ 0) /*A {RD,WR}{FS,GS}BASE instructions */ +XEN_CPUFEATURE(TSC_ADJUST, 5*32+ 1) /*S TSC_ADJUST MSR available */ +XEN_CPUFEATURE(SGX, 5*32+ 2) /* Software Guard extensions */ +XEN_CPUFEATURE(BMI1, 5*32+ 3) /*A 1st bit manipulation extensions */ +XEN_CPUFEATURE(HLE, 5*32+ 4) /*A Hardware Lock Elision */ +XEN_CPUFEATURE(AVX2, 5*32+ 5) /*A AVX2 instructions */ +XEN_CPUFEATURE(FDP_EXCP_ONLY, 5*32+ 6) /*! x87 FDP only updated on exception. */ +XEN_CPUFEATURE(SMEP, 5*32+ 7) /*S Supervisor Mode Execution Protection */ +XEN_CPUFEATURE(BMI2, 5*32+ 8) /*A 2nd bit manipulation extensions */ +XEN_CPUFEATURE(ERMS, 5*32+ 9) /*A Enhanced REP MOVSB/STOSB */ +XEN_CPUFEATURE(INVPCID, 5*32+10) /*H Invalidate Process Context ID */ +XEN_CPUFEATURE(RTM, 5*32+11) /*A Restricted Transactional Memory */ +XEN_CPUFEATURE(PQM, 5*32+12) /* Platform QoS Monitoring */ +XEN_CPUFEATURE(NO_FPU_SEL, 5*32+13) /*! FPU CS/DS stored as zero */ +XEN_CPUFEATURE(MPX, 5*32+14) /*s Memory Protection Extensions */ +XEN_CPUFEATURE(PQE, 5*32+15) /* Platform QoS Enforcement */ +XEN_CPUFEATURE(AVX512F, 5*32+16) /*A AVX-512 Foundation Instructions */ +XEN_CPUFEATURE(AVX512DQ, 5*32+17) /*A AVX-512 Doubleword & Quadword Instrs */ +XEN_CPUFEATURE(RDSEED, 5*32+18) /*A RDSEED instruction */ +XEN_CPUFEATURE(ADX, 5*32+19) /*A ADCX, ADOX instructions */ +XEN_CPUFEATURE(SMAP, 5*32+20) /*S Supervisor Mode Access Prevention */ +XEN_CPUFEATURE(AVX512_IFMA, 5*32+21) /*A AVX-512 Integer Fused Multiply Add */ +XEN_CPUFEATURE(CLFLUSHOPT, 5*32+23) /*A CLFLUSHOPT instruction */ +XEN_CPUFEATURE(CLWB, 5*32+24) /*A CLWB instruction */ +XEN_CPUFEATURE(AVX512PF, 5*32+26) /*A AVX-512 Prefetch Instructions */ +XEN_CPUFEATURE(AVX512ER, 5*32+27) /*A AVX-512 Exponent & Reciprocal Instrs */ +XEN_CPUFEATURE(AVX512CD, 5*32+28) /*A AVX-512 Conflict Detection Instrs */ +XEN_CPUFEATURE(SHA, 5*32+29) /*A SHA1 & SHA256 instructions */ +XEN_CPUFEATURE(AVX512BW, 5*32+30) /*A AVX-512 Byte and Word Instructions */ +XEN_CPUFEATURE(AVX512VL, 5*32+31) /*A AVX-512 Vector Length Extensions */ + +/* Intel-defined CPU features, CPUID level 0x00000007:0.ecx, word 6 */ +XEN_CPUFEATURE(PREFETCHWT1, 6*32+ 0) /*A PREFETCHWT1 instruction */ +XEN_CPUFEATURE(AVX512_VBMI, 6*32+ 1) /*A AVX-512 Vector Byte Manipulation Instrs */ +XEN_CPUFEATURE(UMIP, 6*32+ 2) /*S User Mode Instruction Prevention */ +XEN_CPUFEATURE(PKU, 6*32+ 3) /*H Protection Keys for Userspace */ +XEN_CPUFEATURE(OSPKE, 6*32+ 4) /*! OS Protection Keys Enable */ +XEN_CPUFEATURE(AVX512_VBMI2, 6*32+ 6) /*A Additional AVX-512 Vector Byte Manipulation Instrs */ +XEN_CPUFEATURE(CET_SS, 6*32+ 7) /* CET - Shadow Stacks */ +XEN_CPUFEATURE(GFNI, 6*32+ 8) /*A Galois Field Instrs */ +XEN_CPUFEATURE(VAES, 6*32+ 9) /*A Vector AES Instrs */ +XEN_CPUFEATURE(VPCLMULQDQ, 6*32+10) /*A Vector Carry-less Multiplication Instrs */ +XEN_CPUFEATURE(AVX512_VNNI, 6*32+11) /*A Vector Neural Network Instrs */ +XEN_CPUFEATURE(AVX512_BITALG, 6*32+12) /*A Support for VPOPCNT[B,W] and VPSHUFBITQMB */ +XEN_CPUFEATURE(AVX512_VPOPCNTDQ, 6*32+14) /*A POPCNT for vectors of DW/QW */ +XEN_CPUFEATURE(TSXLDTRK, 6*32+16) /*a TSX load tracking suspend/resume insns */ +XEN_CPUFEATURE(RDPID, 6*32+22) /*A RDPID instruction */ +XEN_CPUFEATURE(CLDEMOTE, 6*32+25) /*A CLDEMOTE instruction */ +XEN_CPUFEATURE(MOVDIRI, 6*32+27) /*a MOVDIRI instruction */ +XEN_CPUFEATURE(MOVDIR64B, 6*32+28) /*a MOVDIR64B instruction */ +XEN_CPUFEATURE(ENQCMD, 6*32+29) /* ENQCMD{,S} instructions */ + +/* AMD-defined CPU features, CPUID level 0x80000007.edx, word 7 */ +XEN_CPUFEATURE(ITSC, 7*32+ 8) /* Invariant TSC */ +XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF Read Only interface */ + +/* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */ +XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */ +XEN_CPUFEATURE(RSTR_FP_ERR_PTRS, 8*32+ 2) /*A (F)X{SAVE,RSTOR} always saves/restores FPU Error pointers */ +XEN_CPUFEATURE(WBNOINVD, 8*32+ 9) /* WBNOINVD instruction */ +XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by AMD) */ +XEN_CPUFEATURE(AMD_PPIN, 8*32+23) /* Protected Processor Inventory Number */ + +/* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */ +XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */ +XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single Precision */ +XEN_CPUFEATURE(SRBDS_CTRL, 9*32+ 9) /* MSR_MCU_OPT_CTRL and RNGDS_MITG_DIS. */ +XEN_CPUFEATURE(MD_CLEAR, 9*32+10) /*A VERW clears microarchitectural buffers */ +XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT */ +XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*a SERIALIZE insn */ +XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking */ +XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */ +XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */ +XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */ +XEN_CPUFEATURE(ARCH_CAPS, 9*32+29) /*a IA32_ARCH_CAPABILITIES MSR */ +XEN_CPUFEATURE(CORE_CAPS, 9*32+30) /* IA32_CORE_CAPABILITIES MSR */ +XEN_CPUFEATURE(SSBD, 9*32+31) /*A MSR_SPEC_CTRL.SSBD available */ + +/* Intel-defined CPU features, CPUID level 0x00000007:1.eax, word 10 */ +XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) /*A AVX512 BFloat16 Instructions */ + +#endif /* XEN_CPUFEATURE */ + +/* Clean up from a default include. Close the enum (for C). */ +#ifdef XEN_CPUFEATURESET_DEFAULT_INCLUDE +#undef XEN_CPUFEATURESET_DEFAULT_INCLUDE +#undef XEN_CPUFEATURE +}; + +#endif /* XEN_CPUFEATURESET_DEFAULT_INCLUDE */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/sys/xen/interface/arch-x86/cpuid.h b/sys/xen/interface/arch-x86/cpuid.h index d709340f18d0..ce46305bee99 100644 --- a/sys/xen/interface/arch-x86/cpuid.h +++ b/sys/xen/interface/arch-x86/cpuid.h @@ -1,8 +1,8 @@ /****************************************************************************** * arch-x86/cpuid.h - * + * * CPUID interface to Xen. - * + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to * deal in the Software without restriction, including without limitation the @@ -20,9 +20,9 @@ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. - * + * * Copyright (c) 2007 Citrix Systems, Inc. - * + * * Authors: * Keir Fraser <keir@xen.org> */ @@ -73,18 +73,46 @@ #define _XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD 0 #define XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD (1u<<0) +/* + * Leaf 4 (0x40000x03) + * Sub-leaf 0: EAX: bit 0: emulated tsc + * bit 1: host tsc is known to be reliable + * bit 2: RDTSCP instruction available + * EBX: tsc_mode: 0=default (emulate if necessary), 1=emulate, + * 2=no emulation, 3=no emulation + TSC_AUX support + * ECX: guest tsc frequency in kHz + * EDX: guest tsc incarnation (migration count) + * Sub-leaf 1: EAX: tsc offset low part + * EBX: tsc offset high part + * ECX: multiplicator for tsc->ns conversion + * EDX: shift amount for tsc->ns conversion + * Sub-leaf 2: EAX: host tsc frequency in kHz + */ + /* * Leaf 5 (0x40000x04) * HVM-specific features - * EAX: Features - * EBX: vcpu id (iff EAX has XEN_HVM_CPUID_VCPU_ID_PRESENT flag) + * Sub-leaf 0: EAX: Features + * Sub-leaf 0: EBX: vcpu id (iff EAX has XEN_HVM_CPUID_VCPU_ID_PRESENT flag) + * Sub-leaf 0: ECX: domain id (iff EAX has XEN_HVM_CPUID_DOMID_PRESENT flag) */ #define XEN_HVM_CPUID_APIC_ACCESS_VIRT (1u << 0) /* Virtualized APIC registers */ #define XEN_HVM_CPUID_X2APIC_VIRT (1u << 1) /* Virtualized x2APIC accesses */ /* Memory mapped from other domains has valid IOMMU entries */ #define XEN_HVM_CPUID_IOMMU_MAPPINGS (1u << 2) #define XEN_HVM_CPUID_VCPU_ID_PRESENT (1u << 3) /* vcpu id is present in EBX */ +#define XEN_HVM_CPUID_DOMID_PRESENT (1u << 4) /* domid is present in ECX */ + +/* + * Leaf 6 (0x40000x05) + * PV-specific parameters + * Sub-leaf 0: EAX: max available sub-leaf + * Sub-leaf 0: EBX: bits 0-7: max machine address width + */ + +/* Max. address width in bits taking memory hotplug into account. */ +#define XEN_CPUID_MACHINE_ADDRESS_WIDTH_MASK (0xffu << 0) -#define XEN_CPUID_MAX_NUM_LEAVES 4 +#define XEN_CPUID_MAX_NUM_LEAVES 5 #endif /* __XEN_PUBLIC_ARCH_X86_CPUID_H__ */ diff --git a/sys/xen/interface/arch-x86/hvm/.save.h.swp b/sys/xen/interface/arch-x86/hvm/.save.h.swp new file mode 100644 index 000000000000..d5f583e519f8 Binary files /dev/null and b/sys/xen/interface/arch-x86/hvm/.save.h.swp differ diff --git a/sys/xen/interface/arch-x86/hvm/save.h b/sys/xen/interface/arch-x86/hvm/save.h index 75ab9b592cdc..773a380bc22b 100644 --- a/sys/xen/interface/arch-x86/hvm/save.h +++ b/sys/xen/interface/arch-x86/hvm/save.h @@ -1,7 +1,7 @@ -/* +/* * Structure definitions for HVM state that is held by Xen and must * be saved along with the domain's memory and device-model state. - * + * * Copyright (c) 2007 XenSource Ltd. * * Permission is hereby granted, free of charge, to any person obtaining a copy @@ -26,8 +26,10 @@ #ifndef __XEN_PUBLIC_HVM_SAVE_X86_H__ #define __XEN_PUBLIC_HVM_SAVE_X86_H__ -/* - * Save/restore header: general info about the save file. +#include "../../xen.h" + +/* + * Save/restore header: general info about the save file. */ #define HVM_FILE_MAGIC 0x54381286 @@ -43,10 +45,13 @@ struct hvm_save_header { DECLARE_HVM_SAVE_TYPE(HEADER, 1, struct hvm_save_header); + /* * Processor * - * Compat: Pre-3.4 didn't have msr_tsc_aux + * Compat: + * - Pre-3.4 didn't have msr_tsc_aux + * - Pre-4.7 didn't have fpu_initialised */ struct hvm_hw_cpu { @@ -82,7 +87,7 @@ struct hvm_hw_cpu { uint64_t dr2; uint64_t dr3; uint64_t dr6; - uint64_t dr7; + uint64_t dr7; uint32_t cs_sel; uint32_t ds_sel; @@ -132,7 +137,7 @@ struct hvm_hw_cpu { uint64_t shadow_gs; /* msr content saved/restored. */ - uint64_t msr_flags; + uint64_t msr_flags; /* Obsolete, ignored. */ uint64_t msr_lstar; uint64_t msr_star; uint64_t msr_cstar; @@ -156,6 +161,11 @@ struct hvm_hw_cpu { }; /* error code for pending event */ uint32_t error_code; + +#define _XEN_X86_FPU_INITIALISED 0 +#define XEN_X86_FPU_INITIALISED (1U<<_XEN_X86_FPU_INITIALISED) + uint32_t flags; + uint32_t pad0; }; struct hvm_hw_cpu_compat { @@ -191,7 +201,7 @@ struct hvm_hw_cpu_compat { uint64_t dr2; uint64_t dr3; uint64_t dr6; - uint64_t dr7; + uint64_t dr7; uint32_t cs_sel; uint32_t ds_sel; @@ -241,7 +251,7 @@ struct hvm_hw_cpu_compat { uint64_t shadow_gs; /* msr content saved/restored. */ - uint64_t msr_flags; + uint64_t msr_flags; /* Obsolete, ignored. */ uint64_t msr_lstar; uint64_t msr_star; uint64_t msr_cstar; @@ -267,18 +277,26 @@ struct hvm_hw_cpu_compat { uint32_t error_code; }; -static inline int _hvm_hw_fix_cpu(void *h) { +static inline int _hvm_hw_fix_cpu(void *h, uint32_t size) { + union hvm_hw_cpu_union { struct hvm_hw_cpu nat; struct hvm_hw_cpu_compat cmp; } *ucpu = (union hvm_hw_cpu_union *)h; - /* If we copy from the end backwards, we should - * be able to do the modification in-place */ - ucpu->nat.error_code = ucpu->cmp.error_code; - ucpu->nat.pending_event = ucpu->cmp.pending_event; - ucpu->nat.tsc = ucpu->cmp.tsc; - ucpu->nat.msr_tsc_aux = 0; + if ( size == sizeof(struct hvm_hw_cpu_compat) ) + { + /* + * If we copy from the end backwards, we should + * be able to do the modification in-place. + */ + ucpu->nat.error_code = ucpu->cmp.error_code; + ucpu->nat.pending_event = ucpu->cmp.pending_event; + ucpu->nat.tsc = ucpu->cmp.tsc; + ucpu->nat.msr_tsc_aux = 0; + } + /* Mimic the old behaviour by unconditionally setting fpu_initialised. */ + ucpu->nat.flags = XEN_X86_FPU_INITIALISED; return 0; } @@ -340,37 +358,50 @@ struct hvm_hw_vpic { DECLARE_HVM_SAVE_TYPE(PIC, 3, struct hvm_hw_vpic); + /* * IO-APIC */ +union vioapic_redir_entry +{ + uint64_t bits; + struct { + uint8_t vector; + uint8_t delivery_mode:3; + uint8_t dest_mode:1; + uint8_t delivery_status:1; + uint8_t polarity:1; + uint8_t remote_irr:1; + uint8_t trig_mode:1; + uint8_t mask:1; + uint8_t reserve:7; + uint8_t reserved[4]; + uint8_t dest_id; + } fields; +}; + #define VIOAPIC_NUM_PINS 48 /* 16 ISA IRQs, 32 non-legacy PCI IRQS. */ -struct hvm_hw_vioapic { - uint64_t base_address; - uint32_t ioregsel; - uint32_t id; - union vioapic_redir_entry - { - uint64_t bits; - struct { - uint8_t vector; - uint8_t delivery_mode:3; - uint8_t dest_mode:1; - uint8_t delivery_status:1; - uint8_t polarity:1; - uint8_t remote_irr:1; - uint8_t trig_mode:1; - uint8_t mask:1; - uint8_t reserve:7; - uint8_t reserved[4]; - uint8_t dest_id; - } fields; - } redirtbl[VIOAPIC_NUM_PINS]; -}; +#define XEN_HVM_VIOAPIC(name, cnt) \ + struct name { \ + uint64_t base_address; \ + uint32_t ioregsel; \ + uint32_t id; \ + union vioapic_redir_entry redirtbl[cnt]; \ + } + +XEN_HVM_VIOAPIC(hvm_hw_vioapic, VIOAPIC_NUM_PINS); + +#ifndef __XEN__ +#undef XEN_HVM_VIOAPIC +#else +#undef VIOAPIC_NUM_PINS +#endif DECLARE_HVM_SAVE_TYPE(IOAPIC, 4, struct hvm_hw_vioapic); + /* * LAPIC */ @@ -390,6 +421,7 @@ struct hvm_hw_lapic_regs { DECLARE_HVM_SAVE_TYPE(LAPIC_REGS, 6, struct hvm_hw_lapic_regs); + /* * IRQs */ @@ -433,7 +465,7 @@ struct hvm_hw_pci_link { DECLARE_HVM_SAVE_TYPE(PCI_LINK, 9, struct hvm_hw_pci_link); -/* +/* * PIT */ @@ -458,9 +490,10 @@ struct hvm_hw_pit { DECLARE_HVM_SAVE_TYPE(PIT, 10, struct hvm_hw_pit); -/* + +/* * RTC - */ + */ #define RTC_CMOS_SIZE 14 struct hvm_hw_rtc { @@ -469,10 +502,13 @@ struct hvm_hw_rtc { /* Index register for 2-part operations */ uint8_t cmos_index; uint8_t pad0; + /* RTC offset from host time */ + int64_t rtc_offset; }; DECLARE_HVM_SAVE_TYPE(RTC, 11, struct hvm_hw_rtc); + /* * HPET */ @@ -502,6 +538,7 @@ struct hvm_hw_hpet { DECLARE_HVM_SAVE_TYPE(HPET, 12, struct hvm_hw_hpet); + /* * PM timer */ @@ -542,12 +579,11 @@ struct hvm_hw_cpu_xsave { struct { struct { char x[512]; } fpu_sse; - struct { *** 12558 LINES SKIPPED ***
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