Date: Tue, 24 Jan 2012 11:10:32 +0000 (UTC) From: Konstantin Belousov <kib@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-9@freebsd.org Subject: svn commit: r230501 - in stable/9/sys: amd64/include i386/include Message-ID: <201201241110.q0OBAWTq072602@svn.freebsd.org>
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Author: kib Date: Tue Jan 24 11:10:32 2012 New Revision: 230501 URL: http://svn.freebsd.org/changeset/base/230501 Log: MFC r230261: Add definitions related to XCR0. Modified: stable/9/sys/amd64/include/specialreg.h stable/9/sys/i386/include/specialreg.h Directory Properties: stable/9/sys/ (props changed) Modified: stable/9/sys/amd64/include/specialreg.h ============================================================================== --- stable/9/sys/amd64/include/specialreg.h Tue Jan 24 11:06:22 2012 (r230500) +++ stable/9/sys/amd64/include/specialreg.h Tue Jan 24 11:10:32 2012 (r230501) @@ -66,6 +66,7 @@ #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ +#define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ /* * Bits in AMD64 special registers. EFER is 64 bits wide. @@ -76,6 +77,18 @@ #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ /* + * Intel Extended Features registers + */ +#define XCR0 0 /* XFEATURE_ENABLED_MASK register */ + +#define XFEATURE_ENABLED_X87 0x00000001 +#define XFEATURE_ENABLED_SSE 0x00000002 +#define XFEATURE_ENABLED_AVX 0x00000004 + +#define XFEATURE_AVX \ + (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX) + +/* * CPUID instruction features register */ #define CPUID_FPU 0x00000001 Modified: stable/9/sys/i386/include/specialreg.h ============================================================================== --- stable/9/sys/i386/include/specialreg.h Tue Jan 24 11:06:22 2012 (r230500) +++ stable/9/sys/i386/include/specialreg.h Tue Jan 24 11:10:32 2012 (r230501) @@ -66,6 +66,7 @@ #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ +#define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ /* * Bits in AMD64 special registers. EFER is 64 bits wide.
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