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charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/stable/15 X-Git-Reftype: branch X-Git-Commit: 565f47e8f47080e0bb89219e04f7e18b68b34e9a Auto-Submitted: auto-generated Date: Mon, 09 Feb 2026 16:28:28 +0000 Message-Id: <698a0b2c.1dcc0.3a35d8d1@gitrepo.freebsd.org> The branch stable/15 has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=565f47e8f47080e0bb89219e04f7e18b68b34e9a commit 565f47e8f47080e0bb89219e04f7e18b68b34e9a Author: Sarah Walker AuthorDate: 2026-01-13 15:26:10 +0000 Commit: Andrew Turner CommitDate: 2026-02-09 14:50:02 +0000 arm64: Add FEAT_MOPS register fields (commit message by andrew@) Reviewed by: andrew Sponsored by: Arm Ltd (cherry picked from commit 0685fc435c2b6750762d50985bc6876dede5fbe2) --- sys/arm64/include/armreg.h | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 27b02c44cd76..28dec3a40b26 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -592,6 +592,27 @@ #define ISS_MSR_REG(reg) \ __ISS_MSR_REG(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) +#define ISS_MOE_MEMINST_SHIFT 24 +#define ISS_MOE_MEMINST (0x01 << ISS_MOE_MEMINST_SHIFT) +#define ISS_MOE_isSETG_SHIFT 24 +#define ISS_MOE_isSETG (0x01 << ISS_MOE_isSETG_SHIFT) +#define ISS_MOE_OPTIONS_SHIFT 19 +#define ISS_MOE_OPTIONS_MASK (0x0f << ISS_MOE_OPTIONS_SHIFT) +#define ISS_MOE_FROM_EPILOGUE_SHIFT 18 +#define ISS_MOE_FROM_EPILOGUE (0x01 << ISS_MOE_FROM_EPILOGUE_SHIFT) +#define ISS_MOE_FORMAT_OPTION_SHIFT 16 +#define ISS_MOE_FORMAT_OPTION_MASK (0x03 << ISS_MOE_FORMAT_OPTION_SHIFT) +#define ISS_MOE_FORMAT_OPTION_B (0x00 << ISS_MOE_FORMAT_OPTION_SHIFT) +#define ISS_MOE_FORMAT_OPTION_A (0x01 << ISS_MOE_FORMAT_OPTION_SHIFT) +#define ISS_MOE_FORMAT_OPTION_A2 (0x02 << ISS_MOE_FORMAT_OPTION_SHIFT) +#define ISS_MOE_FORMAT_OPTION_B2 (0x03 << ISS_MOE_FORMAT_OPTION_SHIFT) +#define ISS_MOE_DESTREG_SHIFT 10 +#define ISS_MOE_DESTREG_MASK (0x1f << ISS_MOE_DESTREG_SHIFT) +#define ISS_MOE_SRCREG_SHIFT 5 +#define ISS_MOE_SRCREG_MASK (0x1f << ISS_MOE_SRCREG_SHIFT) +#define ISS_MOE_SIZEREG_SHIFT 0 +#define ISS_MOE_SIZEREG_MASK (0x1f << ISS_MOE_SIZEREG_SHIFT) + #define ISS_DATA_ISV_SHIFT 24 #define ISS_DATA_ISV (0x01 << ISS_DATA_ISV_SHIFT) #define ISS_DATA_SAS_SHIFT 22 @@ -656,6 +677,7 @@ #define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ #define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ #define EXCP_SP_ALIGN 0x26 /* SP slignment fault */ +#define EXCP_MOE 0x27 /* Memory Operation Exception */ #define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ #define EXCP_SERROR 0x2f /* SError interrupt */ #define EXCP_BRKPT_EL0 0x30 /* Hardware breakpoint, from same EL */ @@ -2627,7 +2649,9 @@ #define SCTLR_LSMAOE (UL(0x1) << 29) #define SCTLR_EnIB (UL(0x1) << 30) #define SCTLR_EnIA (UL(0x1) << 31) -/* Bits 34:32 are reserved */ +/* Bit 32 is reserved */ +#define SCTLR_MSCEn (UL(0x1) << 33) +/* Bit 34 is reserved */ #define SCTLR_BT0 (UL(0x1) << 35) #define SCTLR_BT1 (UL(0x1) << 36) #define SCTLR_ITFSB (UL(0x1) << 37)