From owner-freebsd-current@FreeBSD.ORG Thu Sep 15 21:09:04 2011 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 66336106564A; Thu, 15 Sep 2011 21:09:04 +0000 (UTC) (envelope-from delphij@gmail.com) Received: from mail-gy0-f182.google.com (mail-gy0-f182.google.com [209.85.160.182]) by mx1.freebsd.org (Postfix) with ESMTP id EF9398FC0A; Thu, 15 Sep 2011 21:09:03 +0000 (UTC) Received: by gyf2 with SMTP id 2so3096712gyf.13 for ; Thu, 15 Sep 2011 14:09:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=pxXtA3Bd9m+UIH/ClMq70s0IKOOzGAlxFCzrXtxL0eQ=; b=xaDXpYOI5Loj5yvKWx2xm7m9PsOn3WNYYxayGPX+JZ5PqB+E8s2FeAzjz+Ak4o/yRN 7PinJpnym14laRmKV/Emrobde2s7b1qOgIOTJXVjAAYCTPG6xQPfFOiJQcArJrr7blTd nYUbt7Y1jDxS5ftBofAk0MkAPh88zPj1sBxL8= MIME-Version: 1.0 Received: by 10.150.67.10 with SMTP id p10mr1686682yba.278.1316119358970; Thu, 15 Sep 2011 13:42:38 -0700 (PDT) Received: by 10.150.136.11 with HTTP; Thu, 15 Sep 2011 13:42:38 -0700 (PDT) In-Reply-To: References: <4E72505B.30700@FreeBSD.org> Date: Thu, 15 Sep 2011 13:42:38 -0700 Message-ID: From: Xin LI To: "K. Macy" Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Cc: FreeBSD-Current , Arnaud Lacombe , Andriy Gapon Subject: Re: 9.0-BETA2 do not support SpeedStep on E5420 X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Sep 2011 21:09:04 -0000 On Thu, Sep 15, 2011 at 12:32 PM, K. Macy wrote: [...] > sys/x86/cpufreq/est.c:1008 > > =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Attempt to enable SpeedStep if not currentl= y enabled. */ > =C2=A0 =C2=A0 =C2=A0 =C2=A0msr =3D rdmsr(MSR_MISC_ENABLE); > =C2=A0 =C2=A0 =C2=A0 =C2=A0if ((msr & MSR_SS_ENABLE) =3D=3D 0) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0wrmsr(MSR_MISC_ENA= BLE, msr | MSR_SS_ENABLE); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (bootverbose) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0device_printf(dev, "enabling SpeedStep\n"); > > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Check if the en= able failed. */ > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0msr =3D rdmsr(MSR_= MISC_ENABLE); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if ((msr & MSR_SS_= ENABLE) =3D=3D 0) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0device_printf(dev, "failed to enable SpeedStep\n"); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0return (ENXIO); Looking at the Intel=C2=AE 64 and IA-32 Architectures Software Developer=C2= =92s Manual (section 14.1), I think the code here is right? (I'd expect Linux do the same since the code are mostly the same there). Cheers, --=20 Xin LI https://www.delphij.net/ FreeBSD - The Power to Serve! Live free or die