From owner-freebsd-hackers@FreeBSD.ORG Sat Nov 20 21:04:38 2010 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 703B11065674 for ; Sat, 20 Nov 2010 21:04:38 +0000 (UTC) (envelope-from sergio.g.delreal@gmail.com) Received: from mail-ey0-f182.google.com (mail-ey0-f182.google.com [209.85.215.182]) by mx1.freebsd.org (Postfix) with ESMTP id 080C28FC1A for ; Sat, 20 Nov 2010 21:04:37 +0000 (UTC) Received: by eyb7 with SMTP id 7so3332650eyb.13 for ; Sat, 20 Nov 2010 13:04:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=t0TO8nTXktSlLsodWAr1tT7i+RxspQ98xYPTI8jEvTo=; b=IuPDcyHkAAz4u0EX9sNUeQeWSu2x0eUcUHvMS4rm/c2c7/FDgroKNHzeEViZZZ161I 5St61Mnz+TQZcsXNG+bmuNo8QjOrzm/LVsEzabPcpEDbo2vPjG6TqYqJvFYpY1iiANlq ZtOe05zf56hzNsl1B510Jq3hPk3ndSGxMbg40= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=DlJAQDoclhIsf8Kt2VNbWqxs0sJ6uSJRkIXsJypcaYcAXsrX9oxM1aZqqcbB8qAKid GFxV9v0HSWfGQcALvJRMUnvZCFDCYEQzCfkfucea/MNKbsVful2wpeFcOJwsn55GTWCM Y9pMKjhEZWCgw/obkXz+cWq/lGtfhW/BRJMlI= MIME-Version: 1.0 Received: by 10.213.13.16 with SMTP id z16mr1154740ebz.14.1290285538550; Sat, 20 Nov 2010 12:38:58 -0800 (PST) Received: by 10.213.19.205 with HTTP; Sat, 20 Nov 2010 12:38:58 -0800 (PST) Date: Sat, 20 Nov 2010 15:38:58 -0500 Message-ID: From: =?ISO-8859-1?Q?Sergio_Andr=E9s_G=F3mez_del_Real?= To: freebsd-hackers@freebsd.org Content-Type: text/plain; charset=ISO-8859-1 Subject: Quick i386 question... X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 20 Nov 2010 21:04:38 -0000 If received an interrupt while in protected-mode and paging enabled, is linear address from IDT stored at the idtr translated using the paging-hierarchy structures? I have looked at the interrupt/exception chapter in the corresponding Intel manual but can't find the answer. Maybe I overlooked. Thanks.