From owner-svn-src-head@FreeBSD.ORG Wed Mar 17 15:16:15 2010 Return-Path: Delivered-To: svn-src-head@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 9FA071065679; Wed, 17 Mar 2010 15:16:15 +0000 (UTC) (envelope-from brde@optusnet.com.au) Received: from mail03.syd.optusnet.com.au (mail03.syd.optusnet.com.au [211.29.132.184]) by mx1.freebsd.org (Postfix) with ESMTP id 384FC8FC14; Wed, 17 Mar 2010 15:16:14 +0000 (UTC) Received: from c122-106-169-91.carlnfd1.nsw.optusnet.com.au (c122-106-169-91.carlnfd1.nsw.optusnet.com.au [122.106.169.91]) by mail03.syd.optusnet.com.au (8.13.1/8.13.1) with ESMTP id o2HFG0uv025354 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 18 Mar 2010 02:16:02 +1100 Date: Thu, 18 Mar 2010 02:16:00 +1100 (EST) From: Bruce Evans X-X-Sender: bde@delplex.bde.org To: Andrew Gallatin In-Reply-To: <4BA0CF37.2010903@cs.duke.edu> Message-ID: <20100318015744.B26867@delplex.bde.org> References: <201003161745.o2GHjG3G051630@svn.freebsd.org> <4BA0CF37.2010903@cs.duke.edu> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed Cc: svn-src-head@FreeBSD.org, svn-src-all@FreeBSD.org, src-committers@FreeBSD.org, Pyun YongHyeon Subject: Re: svn commit: r205221 - head/sys/dev/bge X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 17 Mar 2010 15:16:15 -0000 On Wed, 17 Mar 2010, Andrew Gallatin wrote: > Pyun YongHyeon wrote: > >> Revert r205090. >> It's hard to know when the mail box register write will get flushed to >> the hardware and it may take longer. >> Pointed out by: scottl > > I may be mis-reading the code, but it looks like the mailbox > register is in memory space, which should be flushed immediately > unless write-combining is enabled on the region. The bge > driver does not seem to be setting up write combining. > Is the concern that something may enable write combining > behind your back? In that case, a wmb() could act as a > serializing instruction and flush the WC buffers. We want writes to the PCI bus to be efficient. Normally (?) writes to bge registers appear to be several times faster than reads. I don't know if this depends on write combining but think it depends on write buffering which can delay the write to the hardware by about the difference between the read time and the time to write to the bufer. Any forcing of serialization or timing would presumably lose the benefits of the buffer. > Or is it something completely different? Eg, maybe the chip > polls the mailboxes at some regular interval, and it doesn't > notice a write immediately. So writing earlier gives a better chance > that it will see the new value sooner. The old and restored strategy is to write early and then read. The read forces the write to the hardware, so it gives a 100% chance that the hardware sees the write before the read (and before everything that follows the read; accesses to the status block in fact follow the read). Probably these reads take even longer than most PCI reads since they have to wait for the write that was just done, but not much can be done about that except moving the write even earlier and/or moving stuff that doesn't need to be serialized in between the write and the read. Bruce