From owner-svn-src-all@freebsd.org Mon Sep 12 16:38:53 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 4BE46BD7E30; Mon, 12 Sep 2016 16:38:53 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 29E28108; Mon, 12 Sep 2016 16:38:53 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u8CGcqXT000808; Mon, 12 Sep 2016 16:38:52 GMT (envelope-from br@FreeBSD.org) Received: (from br@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u8CGcqmD000805; Mon, 12 Sep 2016 16:38:52 GMT (envelope-from br@FreeBSD.org) Message-Id: <201609121638.u8CGcqmD000805@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: br set sender to br@FreeBSD.org using -f From: Ruslan Bukin Date: Mon, 12 Sep 2016 16:38:52 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r305743 - in head/sys/mips: malta mips X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 12 Sep 2016 16:38:53 -0000 Author: br Date: Mon Sep 12 16:38:51 2016 New Revision: 305743 URL: https://svnweb.freebsd.org/changeset/base/305743 Log: Add SMP support for MTI Malta 34kf CPU. Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Modified: head/sys/mips/malta/asm_malta.S head/sys/mips/malta/malta_mp.c head/sys/mips/mips/locore.S Modified: head/sys/mips/malta/asm_malta.S ============================================================================== --- head/sys/mips/malta/asm_malta.S Mon Sep 12 16:36:44 2016 (r305742) +++ head/sys/mips/malta/asm_malta.S Mon Sep 12 16:38:51 2016 (r305743) @@ -37,6 +37,7 @@ #include #define VPECONF0_MVP (1 << 1) +#define VPECONF0_VPA (1 << 0) .set noreorder @@ -54,16 +55,16 @@ LEAF(platform_processor_id) .set pop END(platform_processor_id) -LEAF(enable_mvp) +LEAF(malta_cpu_configure) .set push .set mips32r2 .set noat - li t2, (VPECONF0_MVP) + li t2, (VPECONF0_MVP | VPECONF0_VPA) move $1, t2 jr ra .word 0x41810000 | (1 << 11) | 2 # mttc0 t2, $1, 2 .set pop -END(enable_mvp) +END(malta_cpu_configure) /* * Called on APs to wait until they are told to launch. Modified: head/sys/mips/malta/malta_mp.c ============================================================================== --- head/sys/mips/malta/malta_mp.c Mon Sep 12 16:36:44 2016 (r305742) +++ head/sys/mips/malta/malta_mp.c Mon Sep 12 16:38:51 2016 (r305743) @@ -49,6 +49,9 @@ __FBSDID("$FreeBSD$"); #include #define MALTA_MAXCPU 2 +#define VPECONF0_VPA (1 << 0) +#define MVPCONTROL_VPC (1 << 1) +#define TCSTATUS_A (1 << 13) unsigned malta_ap_boot = ~0; @@ -62,6 +65,19 @@ unsigned malta_ap_boot = ~0; #define C_IRQ5 (1 << 15) static inline void +evpe(void) +{ + __asm __volatile( + " .set push \n" + " .set noreorder \n" + " .set noat \n" + " .set mips32r2 \n" + " .word 0x41600021 # evpe \n" + " ehb \n" + " .set pop \n"); +} + +static inline void ehb(void) { __asm __volatile( @@ -118,25 +134,30 @@ ehb(void) __retval; \ }) -void -platform_ipi_send(int cpuid) +static void +set_thread_context(int cpuid) { uint32_t reg; - /* - * Set thread context. - * Note this is not global, so we don't need lock. - */ reg = read_c0_register32(1, 1); reg &= ~(0xff); reg |= cpuid; write_c0_register32(1, 1, reg); ehb(); +} + +void +platform_ipi_send(int cpuid) +{ + uint32_t reg; + + set_thread_context(cpuid); /* Set cause */ reg = mftc0(13, 0); - mttc0(13, 0, (reg | C_SW1)); + reg |= (C_SW1); + mttc0(13, 0, reg); } void @@ -204,8 +225,42 @@ platform_smp_topo(void) int platform_start_ap(int cpuid) { + uint32_t reg; int timeout; + /* Enter into configuration */ + reg = read_c0_register32(0, 1); + reg |= (MVPCONTROL_VPC); + write_c0_register32(0, 1, reg); + + set_thread_context(cpuid); + + /* + * Hint: how to set entry point. + * reg = 0x80000000; + * mttc0(2, 3, reg); + */ + + /* Enable thread */ + reg = mftc0(2, 1); + reg |= (TCSTATUS_A); + mttc0(2, 1, reg); + + /* Unhalt CPU core */ + mttc0(2, 4, 0); + + /* Activate VPE */ + reg = mftc0(1, 2); + reg |= (VPECONF0_VPA); + mttc0(1, 2, reg); + + /* Out of configuration */ + reg = read_c0_register32(0, 1); + reg &= ~(MVPCONTROL_VPC); + write_c0_register32(0, 1, reg); + + evpe(); + if (atomic_cmpset_32(&malta_ap_boot, ~0, cpuid) == 0) return (-1); Modified: head/sys/mips/mips/locore.S ============================================================================== --- head/sys/mips/mips/locore.S Mon Sep 12 16:36:44 2016 (r305742) +++ head/sys/mips/mips/locore.S Mon Sep 12 16:38:51 2016 (r305743) @@ -161,7 +161,7 @@ VECTOR(_locore, unknown) #if defined(CPU_MALTA) && defined(SMP) .set push .set mips32r2 - jal enable_mvp + jal malta_cpu_configure nop jal platform_processor_id nop