Date: Sun, 2 Feb 1997 12:51:35 -0700 (MST) From: Terry Lambert <terry@lambert.org> To: narvi@haldjas.folklore.ee (Narvi) Cc: terry@lambert.org, gurney_j@resnet.uoregon.edu, hackers@freefall.freebsd.org Subject: Re: performance puzzler Message-ID: <199702021951.MAA08288@phaeton.artisoft.com> In-Reply-To: <Pine.BSF.3.95.970202201858.13473A-100000@haldjas.folklore.ee> from "Narvi" at Feb 2, 97 08:20:55 pm
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> > The PCI and EISA standards specify 33MHz as their top end. > > Where did I read about 66Mhz revision/mode for PCI? Was it in a dream or > just a "not supported by anybody yet" possibility as is the 64bit card > width. Or was it all just a dream or erroneus news article? The PCI SIG has been discussing this. Obviously, the 64bit version can't use the same edge connector because there aren't 32 free lines; all this "64bit PCI card" hype claimed by video vendors is on-card data path, not bus data path. The 66MHz has also been discussed, but requires a way to key the bus as to which type of card is present so it can introduce a wait state per cycle for older cards. One problem with the design is that the bus chaining used in current Intel chip designs won't work: you can't send 66MHz signals down a bus if you have 33MHz cards potentially listening or attempting to master the bus. This basically means that the Intel PCI bus chips can't tie all the slots to the same chip lines, if you are going to try to use the same card connector. This is a win, in that it means that we will finally get over the 4 slot limit imposed by the line drivers (which doesn't exist in the Motorola and Apple PCI chipsets because they were not lazy in their design). It's bad, because it means new motherboard designs, and PCI has just settled down from the last minor revision to the spec.. 8-(. Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers.
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