Date: Sun, 26 Aug 2012 17:15:26 -0600 From: Warner Losh <imp@bsdimp.com> To: Tim Kientzle <tim@kientzle.com> Cc: freebsd-arm@freebsd.org, freebsd-mips@freebsd.org, "arch@" <freebsd-arch@freebsd.org> Subject: Re: Partial cacheline flush problems on ARM and MIPS Message-ID: <AB7FA4CA-BD70-4799-849D-94EAC8E17F1F@bsdimp.com> In-Reply-To: <DD23C97F-E90D-48A8-9F12-9BADBDDF3D1C@kientzle.com> References: <1345757300.27688.535.camel@revolution.hippie.lan> <3A08EB08-2BBF-4B0F-97F2-A3264754C4B7@bsdimp.com> <1345763393.27688.578.camel@revolution.hippie.lan> <FD8DC82C-AD3B-4EBC-A625-62A37B9ECBF1@bsdimp.com> <1345765503.27688.602.camel@revolution.hippie.lan> <CAJ-VmonOwgR7TNuYGtTOhAbgz-opti_MRJgc8G%2BB9xB3NvPFJQ@mail.gmail.com> <1345766109.27688.606.camel@revolution.hippie.lan> <CAJ-VmomFhqV5rTDf-kKQfbSuW7SSiSnqPEjGPtxWjaHFA046kQ@mail.gmail.com> <F8C9E811-8597-4ED0-9F9D-786EB2301D6F@bsdimp.com> <1346002922.1140.56.camel@revolution.hippie.lan> <CAP%2BM-_HZ4yARwZA2koPJDeJWHT-1LORupjymuVnMtLBzeXe=DA@mail.gmail.com> <DD23C97F-E90D-48A8-9F12-9BADBDDF3D1C@kientzle.com>
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On Aug 26, 2012, at 12:53 PM, Tim Kientzle wrote: >=20 > On Sun, Aug 26, 2012 at 12:42 PM, Ian Lepore > <freebsd@damnhippie.dyndns.org> wrote: >> On Thu, 2012-08-23 at 22:00 -0600, Warner Losh wrote: >>> The bottom line is that you can't mix things like that when cache >>> lines are involved. >>>=20 >> =85. I think we should more explicitly spell out >> what the appropriate sequences are. >=20 >=20 > As someone who is just tinkering with driver code for > the first time, I applaud any attempts to better document > this area! ;-) >=20 >> In particular: >>=20 >> * The PRE and POST operations must occur in pairs; a PREREAD must >> be followed eventually by a POSTREAD and a PREWRITE must be >> followed by a POSTWRITE. >> * The CPU is not allowed to access the mapped memory after a PRE >> sync and before the corresponding POST sync. >> * The DMA hardware is not allowed to access the mapped memory >> after a POST sync and before the next PRE sync. >=20 >=20 > These rules sound reasonable. Good documentation might > also give examples of what the PRE/POST operations might entail > (e.g., from the preceding discussion, it sounds like PREREAD > and PREWRITE require at least a partial cache flush on ARM). > That helps folks who are coming to the docs with some hardware > background. >=20 >> * Read and write sync operators may be combined in a single = call, >> PRE and POST operators may not be. E.G., PREREAD|PREWRITE is >> allowed, PREREAD|POSTREAD is not. We should note that while >> read and write operations may be combined, on some platforms >> PREREAD|PREWRITE is needlessly expensive when only a read is >> being performed. >=20 >=20 > PREREAD|POSTREAD doesn't sound useful to me, but > why would it be explicitly forbidden? It could be useful when DMAing from multiple devices. Let's say I have = a buffer that I want to get data from two different DMA operations. = Wouldn't this be how you'd specify it? > Would you also forbid POSTREAD|PREWRITE? > (For a buffer that has just completed a DMA read > and is going to be immediately used for a DMA write?) This could be useful for some zero-copy things, no? Warner > Tim >=20 > _______________________________________________ > freebsd-arm@freebsd.org mailing list > http://lists.freebsd.org/mailman/listinfo/freebsd-arm > To unsubscribe, send any mail to "freebsd-arm-unsubscribe@freebsd.org"
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