From owner-freebsd-arch@FreeBSD.ORG Tue Jul 25 16:34:06 2006 Return-Path: X-Original-To: freebsd-arch@freebsd.org Delivered-To: freebsd-arch@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 381C816A4DA; Tue, 25 Jul 2006 16:34:05 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from server.baldwin.cx (66-23-211-162.clients.speedfactory.net [66.23.211.162]) by mx1.FreeBSD.org (Postfix) with ESMTP id B25F743D73; Tue, 25 Jul 2006 16:34:04 +0000 (GMT) (envelope-from jhb@freebsd.org) Received: from localhost.corp.yahoo.com (john@localhost [127.0.0.1]) (authenticated bits=0) by server.baldwin.cx (8.13.4/8.13.4) with ESMTP id k6PGY0UE036542; Tue, 25 Jul 2006 12:34:03 -0400 (EDT) (envelope-from jhb@freebsd.org) From: John Baldwin To: "Attilio Rao" Date: Tue, 25 Jul 2006 12:32:50 -0400 User-Agent: KMail/1.9.1 References: <3bbf2fe10607250813w8ff9e34pc505bf290e71758@mail.gmail.com> <3bbf2fe10607250814m1a476f09p2d962dedc0c99be1@mail.gmail.com> In-Reply-To: <3bbf2fe10607250814m1a476f09p2d962dedc0c99be1@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200607251232.51230.jhb@freebsd.org> X-Greylist: Sender succeeded SMTP AUTH authentication, not delayed by milter-greylist-2.0.2 (server.baldwin.cx [127.0.0.1]); Tue, 25 Jul 2006 12:34:04 -0400 (EDT) X-Virus-Scanned: ClamAV 0.87.1/1618/Mon Jul 24 21:12:40 2006 on server.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-4.4 required=4.2 tests=ALL_TRUSTED,AWL,BAYES_00 autolearn=ham version=3.1.0 X-Spam-Checker-Version: SpamAssassin 3.1.0 (2005-09-13) on server.baldwin.cx Cc: freebsd-arch@freebsd.org Subject: Re: [PATCH] Mantaining turnstile aligned to 128 bytes in i386 CPUs X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Jul 2006 16:34:06 -0000 On Tuesday 25 July 2006 11:14, Attilio Rao wrote: > 2006/7/25, Attilio Rao : > > Hi, > > Intel documentation points out that having a 128-bytes aligned > > syncronizing primitive (which fits in a cache line) will minimize the > > traffic for cache bus, so this patch implements an alignment for i386 > > on turnstiles. > > > > Any comments, feedbacks? > > Oh, sorry, I've unforgotten the diff. > > Attilio I think a better approach would be to stick turnstiles (and sleepqueues) in a UMA zone and specify cache-size alignment to the zone. However, turnstiles aren't really sychronization primitives in that you don't spin on a variable inside the structure, and I think it's the spinning and avoiding bouncing cache lines around that Intel's documentation is really about. In that case, the things you want aligned are things like mutexes, rwlocks, etc. -- John Baldwin