From nobody Mon Apr 13 14:24:07 2026 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4fvV5g2GHzz6ZFZ6 for ; Mon, 13 Apr 2026 14:24:07 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R12" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4fvV5g0dCdz3r2T for ; Mon, 13 Apr 2026 14:24:07 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1776090247; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=bFcE2PnXohFv7QzeQhvsi/sU+pKgHbPbAkOOVbJ7uug=; b=GgfhXQ9ondIu7+zrCFjG9cvTAfD+KrELSc/CbzBW3UvWyvk4PGMBo+f9x6zc7pgyq+eX8D F5d6SPuDqFx5xlINoU9bVoAuHaRgOUBkFOTm5yJJiDnzFmU9ukblEZeUaknW6HKSq8w7ln SPPgRRk4CYgPiX/zkF0XV/dZt+8bViCwUBhb4MgO5GSXq1ar3I+JEnF8wo6uFabLeVfu9S lLhvXQ2oRJWl/90rq/Xm4fLoWM8mLrFMfKprtk5hk4wSDq0i8LaV434IBuBDZGqiJXXuOv 6xZAgcmNhW/odO7F+TdGoKK5C8K1IO4ceFRlBzD6P1ycr52s3f2luaIVneALZQ== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1776090247; a=rsa-sha256; cv=none; b=N7l6HfMO9FhokSVtYRWNRhcFAmeRpzmex0lrdFarI9H5QI8RgLXSZ/q0gVz/lPCGi4buCe Lrj8aS1gULMU/pM1SRZk6e+XObBpMfDAfvfWq41aYQP6zBjGB2vSewCgS4SBpk+e8hU+Xf PsDwh3HdGLNWowki96vKzINPEOjDflpwe99MlaMBJnSpG/XqlweWOEgls+Yfg8HLGMXLiI d0hygyer0U25m7xdrdMbQX6p04rAIXlzrUC+5hHmUALRVqRHlacToDdr0PJbvunGhaswG/ 2E/SRdD0ygLuqnuReXcWxSVYAbN1NVOMisUI+31fxQF68V3ulSWcYoB/7bca3g== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1776090247; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=bFcE2PnXohFv7QzeQhvsi/sU+pKgHbPbAkOOVbJ7uug=; b=xmK5OPKk+RnhGt+IWz45DUVNtg3wpAmbZJw6Ym5ZqC0G3CAFvtlOIQBp4soTpTdgokArMt Lk/ZE7jjA0Bi8nGiQIqYyMSXCC4xm6mPO9eEDcet4CUfGDgiUtO80JtZp16vmjFLEFLyun Megi5L9qmnRpFvOGsJDN7WQuRU5j1Q1IxfY80XjQZ+ob+Zzy14AaxNXHZLIzI65KaQQEXi lveaUl4Wv354geGxzChptFchKQSXAJHWx+16BQqW2I8TrRg0AQQdAcX5nXSq8PR5uRnJmo 6yYUf1CcAnrJMfiqbBE0ghG+U5C0YdaUgGW+GbNfiwo3SZrd15dcMn25Q1vu8g== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4fvV5g0Cnsz16hV for ; Mon, 13 Apr 2026 14:24:07 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 4693e by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Mon, 13 Apr 2026 14:24:07 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Cc: Harry Moulton From: Andrew Turner Subject: git: 7e718b9a8eec - main - arm64: mte: cleanup cache register definitions List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 7e718b9a8eec6b5ed86b3b5509fb09dd590a3b60 Auto-Submitted: auto-generated Date: Mon, 13 Apr 2026 14:24:07 +0000 Message-Id: <69dcfc87.4693e.2f93ca58@gitrepo.freebsd.org> The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=7e718b9a8eec6b5ed86b3b5509fb09dd590a3b60 commit 7e718b9a8eec6b5ed86b3b5509fb09dd590a3b60 Author: Harry Moulton AuthorDate: 2026-04-13 11:52:10 +0000 Commit: Andrew Turner CommitDate: 2026-04-13 14:23:05 +0000 arm64: mte: cleanup cache register definitions Cleanup the definitions in armreg.h for the CSSIDR_EL1, CLIDR_EL1 and CSSELR_EL1 system register to prepare for additional bitfeilds for Memory Tagging Extension (MTE). Reviewed by: andrew Sponsored by: Arm Ltd Signed-off-by: Harry Moulton Differential Revision: https://reviews.freebsd.org/D55944 --- sys/arm64/arm64/identcpu.c | 8 ++-- sys/arm64/include/armreg.h | 93 ++++++++++++++++++++++++++++++++++++---------- 2 files changed, 78 insertions(+), 23 deletions(-) diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c index 4b5361090ead..400ea5860695 100644 --- a/sys/arm64/arm64/identcpu.c +++ b/sys/arm64/arm64/identcpu.c @@ -3086,10 +3086,10 @@ print_cpu_cache(struct cpu_desc *desc, struct sbuf *sb, uint64_t ccs, * register. */ if ((desc->id_aa64mmfr2 & ID_AA64MMFR2_CCIDX_64)) - cache_size = (CCSIDR_NSETS_64(ccs) + 1) * - (CCSIDR_ASSOC_64(ccs) + 1); + cache_size = (CCSIDR_NumSets64(ccs) + 1) * + (CCSIDR_Assoc64(ccs) + 1); else - cache_size = (CCSIDR_NSETS(ccs) + 1) * (CCSIDR_ASSOC(ccs) + 1); + cache_size = (CCSIDR_NumSets(ccs) + 1) * (CCSIDR_Assoc(ccs) + 1); cache_size *= line_size; sbuf_printf(sb, "%zuKB (%s)", cache_size / 1024, @@ -3377,7 +3377,7 @@ identify_cpu(u_int cpu) int j = 0; if ((clidr & CLIDR_CTYPE_IO)) { WRITE_SPECIALREG(csselr_el1, - CSSELR_Level(i) | CSSELR_InD); + CSSELR_Level(i) | CSSELR_InD_IC); desc->ccsidr[i][j++] = READ_SPECIALREG(ccsidr_el1); } diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 271fe693cdea..257239b923af 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -167,30 +167,71 @@ #define APIBKeyLo_EL1_op2 2 /* CCSIDR_EL1 - Cache Size ID Register */ -#define CCSIDR_NumSets_MASK 0x0FFFE000 -#define CCSIDR_NumSets64_MASK 0x00FFFFFF00000000 -#define CCSIDR_NumSets_SHIFT 13 -#define CCSIDR_NumSets64_SHIFT 32 -#define CCSIDR_Assoc_MASK 0x00001FF8 -#define CCSIDR_Assoc64_MASK 0x0000000000FFFFF8 +#define CCSIDR_EL1_REG MRS_REG_ALT_NAME(CCSIDR_EL1) +#define CCSIDR_EL1_op0 2 +#define CCSIDR_EL1_op1 1 +#define CCSIDR_EL1_CRn 0 +#define CCSIDR_EL1_CRm 0 +#define CCSIDR_EL1_op2 0 +#define CCSIDR_LineSize_SHIFT 0 +#define CCSIDR_LineSize_WIDTH 3 +#define CCSIDR_LineSize_MASK (UL(0x7) << CCSIDR_LineSize_SHIFT) +#define CCSIDR_LineSize_VAL(x) ((x) & CCSIDR_LineSize_MASK) #define CCSIDR_Assoc_SHIFT 3 +#define CCSIDR_Assoc_WIDTH 10 +#define CCSIDR_Assoc_MASK (UL(0x3ff) << CCSIDR_Assoc_SHIFT) +#define CCSIDR_Assoc_VAL(x) ((x) & CCSIDR_Assoc_MASK) +#define CCSIDR_NumSets_SHIFT 13 +#define CCSIDR_NumSets_WIDTH 15 +#define CCSIDR_NumSets_MASK (UL(0x7fff) << CCSIDR_NumSets_SHIFT) +#define CCSIDR_NumSets_VAL(x) ((x) & CCSIDR_NumSets_MASK) +/* FEAT_CCIDX - Extended Cache Index */ #define CCSIDR_Assoc64_SHIFT 3 -#define CCSIDR_LineSize_MASK 0x7 -#define CCSIDR_NSETS(idr) \ +#define CCSIDR_Assoc64_WIDTH 20 +#define CCSIDR_Assoc64_MASK (UL(0x1fffff) << CCSIDR_Assoc64_SHIFT) +#define CCSIDR_Assoc64_VAL(x) ((x) & CCSIDR_Assoc64_MASK) +#define CCSIDR_NumSets64_SHIFT 32 +#define CCSIDR_NumSets64_WIDTH 23 +#define CCSIDR_NumSets64_MASK (UL(0xffffff) << CCSIDR_NumSets64_SHIFT) +#define CCSIDR_NumSets64_VAL(x) ((x) & CCSIDR_NumSets64_MASK) +#define CCSIDR_NumSets(idr) \ (((idr) & CCSIDR_NumSets_MASK) >> CCSIDR_NumSets_SHIFT) -#define CCSIDR_ASSOC(idr) \ - (((idr) & CCSIDR_Assoc_MASK) >> CCSIDR_Assoc_SHIFT) -#define CCSIDR_NSETS_64(idr) \ +#define CCSIDR_NumSets64(idr) \ (((idr) & CCSIDR_NumSets64_MASK) >> CCSIDR_NumSets64_SHIFT) -#define CCSIDR_ASSOC_64(idr) \ +#define CCSIDR_Assoc(idr) \ + (((idr) & CCSIDR_Assoc_MASK) >> CCSIDR_Assoc_SHIFT) +#define CCSIDR_Assoc64(idr) \ (((idr) & CCSIDR_Assoc64_MASK) >> CCSIDR_Assoc64_SHIFT) /* CLIDR_EL1 - Cache level ID register */ -#define CLIDR_CTYPE_MASK 0x7 /* Cache type mask bits */ -#define CLIDR_CTYPE_IO 0x1 /* Instruction only */ -#define CLIDR_CTYPE_DO 0x2 /* Data only */ -#define CLIDR_CTYPE_ID 0x3 /* Split instruction and data */ -#define CLIDR_CTYPE_UNIFIED 0x4 /* Unified */ +#define CLIDR_EL1_REG MRS_REG_ALT_NAME(CLIDR_EL1) +#define CLIDR_EL1_op0 2 +#define CLIDR_EL1_op1 1 +#define CLIDR_EL1_CRn 0 +#define CLIDR_EL1_CRm 0 +#define CLIDR_EL1_op2 1 +#define CLIDR_CTYPE_MASK UL(0x7) +#define CLIDR_CTYPE_NONE 0x0 /* No cache */ +#define CLIDR_CTYPE_IC 0x1 /* Instruction cache only */ +#define CLIDR_CTYPE_DC 0x2 /* Data cache only */ +#define CLIDR_CTYPE_IO 0x3 /* Separate instruction & data cache */ +#define CLIDR_CTYPE_UNIFIED 0x4 /* Unified cache */ +#define CLIDR_LoUIS_SHIFT 21 +#define CLIDR_LoUIS_WIDTH 3 +#define CLIDR_LoUIS_MASK (UL(0x7) << CLIDR_LoUIS_SHIFT) +#define CLIDR_LoUIS_VAL(x) ((x) & CLIDR_LoUIS_MASK) +#define CLIDR_LoC_SHIFT 24 +#define CLIDR_LoC_WIDTH 3 +#define CLIDR_LoC_MASK (UL(0x7) << CLIDR_LoC_SHIFT) +#define CLIDR_LoC_VAL(x) ((x) & CLIDR_LoC_MASK) +#define CLIDR_LoUU_SHIFT 27 +#define CLIDR_LoUU_WIDTH 3 +#define CLIDR_LoUU_MASK (UL(0x7) << CLIDR_LoUU_SHIFT) +#define CLIDR_LoUU_VAL(x) ((x) & CLIDR_LoUU_MASK) +#define CLIDR_ICB_SHIFT 30 +#define CLIDR_ICB_WIDTH 3 +#define CLIDR_ICB_MASK (UL(0x7) << CLIDR_ICB_SHIFT) +#define CLIDR_ICB_VAL(x) ((x) & CLIDR_ICB_MASK) /* CNTKCTL_EL1 - Counter-timer Kernel Control Register */ #define CNTKCTL_EL1_op0 3 @@ -342,8 +383,22 @@ #define CPACR_EL12_op2 2 /* CSSELR_EL1 - Cache size selection register */ -#define CSSELR_Level(i) (i << 1) -#define CSSELR_InD 0x00000001 +#define CSSELR_EL1_REG MRS_REG_ALT_NAME(CSSELR_EL1) +#define CSSELR_EL1_op0 3 +#define CSSELR_EL1_op1 2 +#define CSSELR_EL1_CRn 0 +#define CSSELR_EL1_CRm 0 +#define CSSELR_EL1_op2 0 +#define CSSELR_InD_SHIFT 0 +#define CSSELR_InD_WIDTH 1 +#define CSSELR_InD_MASK (UL(0x1) << CSSELR_InD_SHIFT) +#define CSSELR_InD_VAL(x) ((x) & CSSELR_InD_MASK) +#define CSSELR_InD_DC (0x0 << CSSELR_InD_SHIFT) /* Data or unified cache */ +#define CSSELR_InD_IC (0x1 << CSSELR_InD_SHIFT) /* Instruction cache */ +#define CSSELR_Level_SHIFT 1 +#define CSSELR_Level_WIDTH 3 +#define CSSELR_Level_MASK (UL(0x7) << CSSELR_Level_SHIFT) +#define CSSELR_Level(i) (i << CSSELR_Level_SHIFT) /* CTR_EL0 - Cache Type Register */ #define CTR_EL0_REG MRS_REG_ALT_NAME(CTR_EL0)