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Date: Wed, 30 Aug 1995 07:49:56 +1000
From: Bruce Evans <bde@zeta.org.au>
Message-Id: <199508292149.HAA02386@godzilla.zeta.org.au>
To: leo@lisa.rur.com, rgrimes@gndrsh.aac.dev.com
Subject: Re: S.O.S -2.1Stable and ASUSP54TP4
Cc: freebsd-hackers@FreeBSD.ORG, jbryant@argus.iadfw.net, rashid@haven.ios.com
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>And to state my reason for agreement that parity is a ``itsy-bitsy comfort'',
>think about the fact that 80% of your memory access are going to a L2
>cache that has never had parity on it, yet has a same FIT rate as the
>main memory system.  Basically your more likely today to take a single
>bit error in your cache as you are in main memory :-(.

Is there anything to detect or correct errors in the registers or
control logic?

Bruce