From owner-freebsd-arm@FreeBSD.ORG Sun Sep 29 20:07:07 2013 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id 0AF77B17; Sun, 29 Sep 2013 20:07:07 +0000 (UTC) (envelope-from bernd@cicely.de) Received: from raven.bwct.de (raven.bwct.de [85.159.14.73]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 92149269E; Sun, 29 Sep 2013 20:07:06 +0000 (UTC) Received: from mail.cicely.de ([10.1.1.37]) by raven.bwct.de (8.13.4/8.13.4) with ESMTP id r8TK6wQ7048865 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=FAIL); Sun, 29 Sep 2013 22:06:58 +0200 (CEST) (envelope-from bernd@cicely.de) Received: from [10.1.11.7] (ipad.cicely.de [10.1.11.7]) by mail.cicely.de (8.14.5/8.14.4) with ESMTP id r8TK6uUF053205 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NO); Sun, 29 Sep 2013 22:06:56 +0200 (CEST) (envelope-from bernd@cicely.de) References: In-Reply-To: Mime-Version: 1.0 (1.0) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=us-ascii Message-Id: <4E82854E-5979-40CD-BA9E-BD72D726E000@cicely.de> X-Mailer: iPad Mail (10B329) From: Bernd Walter Subject: Re: BBB CPU clock (was: Re: FreeBSD on Cubieboard 2, UDOO and Galaxy Note 10.1 (Exynos). Date: Sun, 29 Sep 2013 22:06:57 +0200 To: Jia-Shiun Li X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00=-1.9, MIME_QP_LONG_LINE=0.001, T_RP_MATCHES_RCVD=-0.01 autolearn=ham version=3.3.0 X-Spam-Checker-Version: SpamAssassin 3.3.0 (2010-01-18) on spamd.cicely.de Cc: "freebsd-arm@freebsd.org" , "ticso@cicely.de" X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 29 Sep 2013 20:07:07 -0000 Am 29.09.2013 um 22:01 schrieb Jia-Shiun Li : > On Mon, Sep 30, 2013 at 12:41 AM, Jia-Shiun Li wrote:= >> But I manually modified registers using the sequence in mpu_pll_config() o= f >> u-boot and got the MPU clocked at the value I gave. There seems to be som= e >> unknown sequences in u-boot either skipping or overwriting MPU PLL settin= gs. >=20 > Never mind. Have to copy MLO in addition to u-boot.img as well. > Looks like PLL init part is there. >=20 > However, I cannot set MPU clock to 800 MHz and beyond. Now booting ok at > 750MHz. Maybe a heat sink or active cooling is required. Will try when > I get one. That matches with what the NetBSD list describes. You also need to configure the PMIC to deliver a higher core voltage for higher frequencies. If you don't your systems becomes unstable. > cpufreq for ARM boards may be possible provided frequency can be changed > dynamically. But if the board cannot provide a way to determine > stability reliability it may be impractical to make it automatic. >=20