From owner-freebsd-mips@FreeBSD.ORG Tue Jan 6 03:47:20 2015 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id E04457BE; Tue, 6 Jan 2015 03:47:19 +0000 (UTC) Received: from mail-wi0-x22a.google.com (mail-wi0-x22a.google.com [IPv6:2a00:1450:400c:c05::22a]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G2" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 82B9B25C2; Tue, 6 Jan 2015 03:47:19 +0000 (UTC) Received: by mail-wi0-f170.google.com with SMTP id bs8so5320355wib.3; Mon, 05 Jan 2015 19:47:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date:message-id:subject :from:to:cc:content-type:content-transfer-encoding; bh=QMO/5WC2dCTls3MpZJLlJY1VzVT+Tag0Qdz8p1v6LSA=; b=HlYTWvjReaLYsnF7hg7JdN+rTsHOlYurT2I9O3fS1aFdy0JCcwWhaVVa3OG2EOd6sZ EiKc60SLVBI2Vl2ZyHVBmerqCALlHBGnjScP0++Dp/IuQZy5o3T22hyvdUAHVcvpa3Ar 3Kv0INa22j9WCTXkTp4zJnXLZFr9efWD6zXo0sumQRimxek/8Cmn7fj6uU+WeEFN5n/U g8CcSw54vCO1uwVlLfc3iTOCkCT0WAaNr1vkQexetkSWJy5oyxADmirilOWjmJekH6uA yVk8CxDvMjAHlLRh6kJPbPEYq64NQQvJ9RiBrXjVfGDo+JwlhTnhcQgknxM6W9sRFd0B LtUg== MIME-Version: 1.0 X-Received: by 10.180.20.6 with SMTP id j6mr31705715wie.59.1420516037881; Mon, 05 Jan 2015 19:47:17 -0800 (PST) Sender: adrian.chadd@gmail.com Received: by 10.216.41.136 with HTTP; Mon, 5 Jan 2015 19:47:17 -0800 (PST) In-Reply-To: <3AB1B833-6D17-44C4-B588-8CEAB0CA4A42@bsdimp.com> References: <5F7CBB50-6C91-49C9-BF69-301496DDE792@bsdimp.com> <9F6D585C-7590-4D25-879B-A76D8A959E01@bsdimp.com> <1420514079.14601.7.camel@freebsd.org> <3AB1B833-6D17-44C4-B588-8CEAB0CA4A42@bsdimp.com> Date: Mon, 5 Jan 2015 19:47:17 -0800 X-Google-Sender-Auth: Gu-iSiXPCDhwYAdjE4uuRd_GFiI Message-ID: Subject: Re: interrupt muxes, bus memory space and other fun amusing things From: Adrian Chadd To: Warner Losh Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Cc: Warner Losh , John Baldwin , Ian Lepore , "freebsd-mips@freebsd.org" X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Jan 2015 03:47:20 -0000 Well i'm happy to do it in two pieces: * do whatever to get it up and working so I can do the rest of the qca mips bringups so we get access to like 50 new routers that are out there right now; * take the mips, ppc and arm bits and drive home the unified front, now that we have all the pieces in place and things work. -adrian On 5 January 2015 at 19:26, Warner Losh wrote: > >> On Jan 5, 2015, at 8:14 PM, Ian Lepore wrote: >> >> On Mon, 2015-01-05 at 20:10 -0700, Warner Losh wrote: >>>> On Jan 5, 2015, at 1:31 PM, Adrian Chadd wrote: >>>> >>>> On 5 January 2015 at 08:41, Warner Losh wrote: >>>>> >>>>>> So if I were Linux, I'd just implement a mux that pretends to trigge= r >>>>>> interrupts in a much bigger IRQ space. Ie, they map IP0..IP7 to >>>>>> irq0..7, then they pick another IRQ range for the AHB interrupts, an= d >>>>>> another IRQ range for the IP2/IP3 interrupt mux. They have a >>>>>> hard-coded mux that takes care of triggering the software IRQ based = on >>>>>> the hardware interrupt and mux register contents. >>>>>> >>>>>> So, how should I approach this? >>>>> >>>>> Same way. You=E2=80=99d create an interrupt device that registers an = interrupt >>>>> for the mux, then farms it out based on the contents of the registers= . >>>>> The MIPS interrupt handler might need some work (arm did) to >>>>> allow this to happen, but it isn=E2=80=99t super difficult (though II= Rc it is tedious). >>>> >>>> Ok. So I can do that, but then devices hang off of which bus? nexus0? >>>> Or this mux? >>>> >>>> Can I create a mux bus to hang things off of that just pass all the >>>> memory region requests up to the parent bus (nexus in this case) ? >>> >>> The hard part is mapping an interrupt provided by a mux to a resource >>> number. However, we already do this for the =E2=80=98hard wired=E2=80= =99 interrupts >>> that are muxed through APIC or PIC controllers on x86. I fail to see ho= w >>> this is any different, apart (perhaps) from the need to do things dynam= ically >>> in some way. >>> >>> Warner >>> >> >> It sounds like mips is ready for intrng. Which would then give us ppc, >> arm, and mips all with a conceptually-similar intrng-like layer for >> handling non-hierarchical interrupt sources and controllers and mapping >> between rman and hardware ideas of interrupt number. Hmmm. This would >> be the time to argue for a nice shiny new MI intrng implementation... >> except that we can't quite drive even the arm-only version to >> completion. > > Maybe now=E2=80=99s the time? > > Warner