From owner-svn-src-all@FreeBSD.ORG Tue Oct 5 07:42:00 2010 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 66057106566B; Tue, 5 Oct 2010 07:42:00 +0000 (UTC) (envelope-from jchandra@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 53D6E8FC41; Tue, 5 Oct 2010 07:42:00 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o957g0em045047; Tue, 5 Oct 2010 07:42:00 GMT (envelope-from jchandra@svn.freebsd.org) Received: (from jchandra@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o957g0bG045045; Tue, 5 Oct 2010 07:42:00 GMT (envelope-from jchandra@svn.freebsd.org) Message-Id: <201010050742.o957g0bG045045@svn.freebsd.org> From: "Jayachandran C." Date: Tue, 5 Oct 2010 07:42:00 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r213448 - head/sys/mips/rmi X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Oct 2010 07:42:00 -0000 Author: jchandra Date: Tue Oct 5 07:41:59 2010 New Revision: 213448 URL: http://svn.freebsd.org/changeset/base/213448 Log: Network driver support for more XLR/XLS chip versions. Obtained from: Sriram Gorti (srgorti at netlogicmicro dot com) Modified: head/sys/mips/rmi/board.c Modified: head/sys/mips/rmi/board.c ============================================================================== --- head/sys/mips/rmi/board.c Tue Oct 5 07:21:14 2010 (r213447) +++ head/sys/mips/rmi/board.c Tue Oct 5 07:41:59 2010 (r213448) @@ -62,6 +62,88 @@ xlr_pcmcia_present(void) } static void +xlr_chip_specific_overrides(struct xlr_board_info* board) +{ + struct xlr_gmac_block_t *blk0, *blk1, *blk2; + uint32_t chipid; + uint32_t revision; + + blk0 = &board->gmac_block[0]; + blk1 = &board->gmac_block[1]; + blk2 = &board->gmac_block[2]; + + chipid = xlr_processor_id(); + revision = xlr_revision(); + + if (revision == 0x04) { /* B2 */ + switch (chipid) { + case 0x07: /* XLR 508 */ + case 0x08: /* XLR 516 */ + case 0x09: /* XLR 532 */ + /* NA[12] not available */ + memset(blk1, 0, sizeof(*blk1)); + memset(blk2, 0, sizeof(*blk2)); + break; + case 0x06: /* XLR 308 */ + /* NA0 has 3 ports */ + blk0->gmac_port[3].valid = 0; + blk0->num_ports--; + /* NA[12] not available */ + memset(blk1, 0, sizeof(*blk1)); + memset(blk2, 0, sizeof(*blk2)); + break; + default: + break; + } + } else if (revision == 0x91) { /* C4 */ + switch (chipid) { + case 0x0B: /* XLR 508 */ + case 0x0A: /* XLR 516 */ + case 0x08: /* XLR 532 */ + /* NA[12] not available */ + memset(blk1, 0, sizeof(*blk1)); + memset(blk2, 0, sizeof(*blk2)); + break; + case 0x0F: /* XLR 308 */ + /* NA0 has 3 ports */ + blk0->gmac_port[3].valid = 0; + blk0->num_ports--; + /* NA[12] not available */ + memset(blk1, 0, sizeof(*blk1)); + memset(blk2, 0, sizeof(*blk2)); + break; + default: + break; + } + } else { /* other pre-production silicon */ + switch (chipid) { + /* XLR 5xx */ + case 0x0B: + case 0x0A: + case 0x07: + case 0x08: + case 0x09: + /* NA[12] not available */ + memset(blk1, 0, sizeof(*blk1)); + memset(blk2, 0, sizeof(*blk2)); + break; + /* XLR 3xx */ + case 0x0F: + case 0x06: + /* NA0 has 3 ports */ + blk0->gmac_port[3].valid = 0; + blk0->num_ports--; + /* NA[12] not available */ + memset(blk1, 0, sizeof(*blk1)); + memset(blk2, 0, sizeof(*blk2)); + break; + default: + break; + } + } +} + +static void xlr_board_specific_overrides(struct xlr_board_info* board) { struct xlr_gmac_block_t *blk1, *blk2; @@ -116,6 +198,35 @@ quad1_xaui(void) } static void +xls_chip_specific_overrides(struct xlr_board_info* board) +{ + struct xlr_gmac_block_t *blk0, *blk1; + uint32_t chipid; + + blk0 = &board->gmac_block[0]; + blk1 = &board->gmac_block[1]; + chipid = xlr_processor_id(); + + switch (chipid) { + case 0x8E: /* XLS208 */ + case 0x8F: /* XLS204 */ + /* NA1 is not available */ + memset(blk1, 0, sizeof(*blk1)); + break; + case 0xCE: /* XLS108 */ + case 0xCF: /* XLS104 */ + /* NA0 has 3 ports */ + blk0->gmac_port[3].valid = 0; + blk0->num_ports--; + /* NA1 is not available */ + memset(blk1, 0, sizeof(*blk1)); + break; + default: + break; + } +} + +static void xls_board_specific_overrides(struct xlr_board_info* board) { struct xlr_gmac_block_t *blk0, *blk1; @@ -172,22 +283,15 @@ xls_board_specific_overrides(struct xlr_ break; case RMI_XLR_BOARD_ARIZONA_VIII: - /* There is just one Octal PHY on the board and it is - * connected to the MII interface for NA Quad 0. */ - blk1->gmac_port[0].mii_addr = XLR_IO_GMAC_0_OFFSET; - blk1->gmac_port[1].mii_addr = XLR_IO_GMAC_0_OFFSET; - blk1->gmac_port[2].mii_addr = XLR_IO_GMAC_0_OFFSET; - blk1->gmac_port[3].mii_addr = XLR_IO_GMAC_0_OFFSET; - /* Board 8.3 (Lite) has XLS108 */ - if (xlr_boot1_info.board_minor_version == 3) { - /* NA0 has 3 ports */ - blk0->gmac_port[3].valid = 1; - blk0->num_ports--; - /* NA1 is completely disabled */ - blk1->enabled = 0; + if (blk1->enabled) { + /* There is just one Octal PHY on the board and it is + * connected to the MII interface for NA Quad 0. */ + blk1->gmac_port[0].mii_addr = XLR_IO_GMAC_0_OFFSET; + blk1->gmac_port[1].mii_addr = XLR_IO_GMAC_0_OFFSET; + blk1->gmac_port[2].mii_addr = XLR_IO_GMAC_0_OFFSET; + blk1->gmac_port[3].mii_addr = XLR_IO_GMAC_0_OFFSET; } - break; case RMI_XLR_BOARD_ARIZONA_XI: @@ -285,16 +389,20 @@ xlr_board_info_setup() * if (CPU is XLS) { * // initialize per XLS architecture * // default inits (per chip spec) + * // chip-specific overrides * // board-specific overrides * } else if (CPU is XLR) { * // initialize per XLR architecture * // default inits (per chip spec) + * // chip-specific overrides * // board-specific overrides * } * - * Within each CPU-specific initialization, all the default - * initializations are done first. This is followed up with - * board specific overrides. + * For each CPU family, all the default initializations + * are done for a fully-loaded device of that family. + * This configuration is then adjusted for the actual + * chip id. This is followed up with board specific + * overrides. */ /* start with a clean slate */ @@ -377,6 +485,7 @@ xlr_board_info_setup() /* ---------------- Network Acc 2 ---------------- */ xlr_board_info.gmac_block[2].enabled = 0; /* disabled on XLS */ + xls_chip_specific_overrides(&xlr_board_info); xls_board_specific_overrides(&xlr_board_info); } else { /* XLR */ @@ -456,7 +565,9 @@ xlr_board_info_setup() blk2->gmac_port[0].tx_bucket_id = blk2->station_txbase; blk2->gmac_port[0].mdint_id = 2; - /* Done with default setup. Now do board-specific tweaks. */ + /* Done with default setup. Now handle chip and board-specific + variations. */ + xlr_chip_specific_overrides(&xlr_board_info); xlr_board_specific_overrides(&xlr_board_info); } return 0;