From owner-p4-projects@FreeBSD.ORG Thu Aug 21 07:40:31 2003 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 1FCE416A4ED; Thu, 21 Aug 2003 07:40:30 -0700 (PDT) Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id DD5DD16A4BF for ; Thu, 21 Aug 2003 07:40:25 -0700 (PDT) Received: from mail.speakeasy.net (mail15.speakeasy.net [216.254.0.215]) by mx1.FreeBSD.org (Postfix) with ESMTP id CD26C43FBF for ; Thu, 21 Aug 2003 07:40:24 -0700 (PDT) (envelope-from jhb@FreeBSD.org) Received: (qmail 11424 invoked from network); 21 Aug 2003 14:40:24 -0000 Received: from unknown (HELO server.baldwin.cx) ([216.27.160.63]) (envelope-sender )encrypted SMTP for ; 21 Aug 2003 14:40:24 -0000 Received: from laptop.baldwin.cx (gw1.twc.weather.com [216.133.140.1]) by server.baldwin.cx (8.12.9/8.12.9) with ESMTP id h7LEeM9s098850; Thu, 21 Aug 2003 10:40:22 -0400 (EDT) (envelope-from jhb@FreeBSD.org) Message-ID: X-Mailer: XFMail 1.5.4 on FreeBSD X-Priority: 3 (Normal) Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 8bit MIME-Version: 1.0 In-Reply-To: <200308210731.h7L7V0tt040658@repoman.freebsd.org> Date: Thu, 21 Aug 2003 10:40:47 -0400 (EDT) From: John Baldwin To: Marcel Moolenaar cc: Perforce Change Reviews Subject: RE: PERFORCE change 36551 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Aug 2003 14:40:31 -0000 On 21-Aug-2003 Marcel Moolenaar wrote: > http://perforce.freebsd.org/chv.cgi?CH=36551 > > Change 36551 by marcel@marcel_nfs on 2003/08/21 00:30:38 > > Aarrgghh. The interrupt issue on pluto1 and pluto2 are > very likely not driver problems. I forgot we have a hack > on the ia64 branch to deal with the fact that the non- > legacy interrupts used by the UARTs are edge sensitive, > active high. We really need to get that fixed in CVS... > > Affected files ... > > .. //depot/projects/uart/ia64/ia64/interrupt.c#4 edit > > Differences ... > > ==== //depot/projects/uart/ia64/ia64/interrupt.c#4 (text+ko) ==== > > @@ -266,9 +266,18 @@ > struct sapic *sa = ia64_sapics[i]; > if (irq < sa->sa_base || irq > sa->sa_limit) > continue; > + /* > + * KLUDGE: Not all interrupts higher or equal to 16 are > + * active low and level sensitive. We don't know yet how > + * to check for this, so we hardcode the 2 cases we have > + * wrong explicitly. This kludge is specific to the HP > + * rx2600... > + */ Have you tried looking at any interrupt overrides in the MADT? That is where the BIOS should tell you which interrupts above 15 have ISA-like parameters. > sapic_enable(sa, irq - sa->sa_base, vector, > - (irq < 16) ? SAPIC_TRIGGER_EDGE : SAPIC_TRIGGER_LEVEL, > - (irq < 16) ? SAPIC_POLARITY_HIGH : SAPIC_POLARITY_LOW); > + ((irq < 16 || vector == 66 || vector == 67) > + ? SAPIC_TRIGGER_EDGE : SAPIC_TRIGGER_LEVEL), > + ((irq < 16 || vector == 66 || vector == 67) > + ? SAPIC_POLARITY_HIGH : SAPIC_POLARITY_LOW)); > } > } > -- John Baldwin <>< http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve!" - http://www.FreeBSD.org/