From owner-svn-src-stable-7@FreeBSD.ORG Fri Mar 11 14:55:23 2011 Return-Path: Delivered-To: svn-src-stable-7@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id BF93B106566B; Fri, 11 Mar 2011 14:55:23 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 93ACD8FC18; Fri, 11 Mar 2011 14:55:23 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id p2BEtNj4082166; Fri, 11 Mar 2011 14:55:23 GMT (envelope-from avg@svn.freebsd.org) Received: (from avg@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id p2BEtNHZ082162; Fri, 11 Mar 2011 14:55:23 GMT (envelope-from avg@svn.freebsd.org) Message-Id: <201103111455.p2BEtNHZ082162@svn.freebsd.org> From: Andriy Gapon Date: Fri, 11 Mar 2011 14:55:23 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-7@freebsd.org X-SVN-Group: stable-7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r219487 - in stable/7/sys: amd64/include i386/i386 i386/include X-BeenThere: svn-src-stable-7@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for only the 7-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Mar 2011 14:55:23 -0000 Author: avg Date: Fri Mar 11 14:55:23 2011 New Revision: 219487 URL: http://svn.freebsd.org/changeset/base/219487 Log: MFC r215523: specialreg.h: add AMD-specific "Hardware Configuration Register" MSR Modified: stable/7/sys/amd64/include/specialreg.h stable/7/sys/i386/i386/initcpu.c stable/7/sys/i386/include/specialreg.h Directory Properties: stable/7/sys/ (props changed) stable/7/sys/cddl/contrib/opensolaris/ (props changed) stable/7/sys/contrib/dev/acpica/ (props changed) stable/7/sys/contrib/pf/ (props changed) Modified: stable/7/sys/amd64/include/specialreg.h ============================================================================== --- stable/7/sys/amd64/include/specialreg.h Fri Mar 11 14:53:34 2011 (r219486) +++ stable/7/sys/amd64/include/specialreg.h Fri Mar 11 14:55:23 2011 (r219487) @@ -494,6 +494,7 @@ #define MSR_PERFCTR2 0xc0010006 #define MSR_PERFCTR3 0xc0010007 #define MSR_SYSCFG 0xc0010010 +#define MSR_HWCR 0xc0010015 #define MSR_IORRBASE0 0xc0010016 #define MSR_IORRMASK0 0xc0010017 #define MSR_IORRBASE1 0xc0010018 Modified: stable/7/sys/i386/i386/initcpu.c ============================================================================== --- stable/7/sys/i386/i386/initcpu.c Fri Mar 11 14:53:34 2011 (r219486) +++ stable/7/sys/i386/i386/initcpu.c Fri Mar 11 14:55:23 2011 (r219487) @@ -680,7 +680,7 @@ initializecpu(void) (cpu_id & ~0xf) == 0x670 || (cpu_id & ~0xf) == 0x680)) { u_int regs[4]; - wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000); + wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000); do_cpuid(1, regs); cpu_feature = regs[3]; } Modified: stable/7/sys/i386/include/specialreg.h ============================================================================== --- stable/7/sys/i386/include/specialreg.h Fri Mar 11 14:53:34 2011 (r219486) +++ stable/7/sys/i386/include/specialreg.h Fri Mar 11 14:55:23 2011 (r219487) @@ -544,7 +544,8 @@ #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ /* AMD64 MSR's */ -#define MSR_EFER 0xc0000080 /* extended features */ +#define MSR_EFER 0xc0000080 /* extended features */ +#define MSR_HWCR 0xc0010015 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ #define MSR_MC0_CTL_MASK 0xc0010044