From owner-svn-src-all@FreeBSD.ORG Mon Feb 17 02:24:59 2014 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 0F9A22CE; Mon, 17 Feb 2014 02:24:59 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id EC2E615C8; Mon, 17 Feb 2014 02:24:58 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s1H2OwpL085129; Mon, 17 Feb 2014 02:24:58 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s1H2Owv8085127; Mon, 17 Feb 2014 02:24:58 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201402170224.s1H2Owv8085127@svn.freebsd.org> From: Adrian Chadd Date: Mon, 17 Feb 2014 02:24:58 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r262010 - head/sys/dev/etherswitch/arswitch X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 17 Feb 2014 02:24:59 -0000 Author: adrian Date: Mon Feb 17 02:24:58 2014 New Revision: 262010 URL: http://svnweb.freebsd.org/changeset/base/262010 Log: Implement PHY bus MMD writes for arswitch. This is used by the AR8327 PHY setup path. Obtained from: OpenWRT Modified: head/sys/dev/etherswitch/arswitch/arswitch_reg.c head/sys/dev/etherswitch/arswitch/arswitchreg.h Modified: head/sys/dev/etherswitch/arswitch/arswitch_reg.c ============================================================================== --- head/sys/dev/etherswitch/arswitch/arswitch_reg.c Mon Feb 17 01:40:33 2014 (r262009) +++ head/sys/dev/etherswitch/arswitch/arswitch_reg.c Mon Feb 17 02:24:58 2014 (r262010) @@ -111,6 +111,16 @@ arswitch_writedbg(device_t dev, int phy, MII_ATH_DBG_DATA, dbg_data); } +void +arswitch_writemmd(device_t dev, int phy, uint16_t dbg_addr, + uint16_t dbg_data) +{ + (void) MDIO_WRITEREG(device_get_parent(dev), phy, + MII_ATH_MMD_ADDR, dbg_addr); + (void) MDIO_WRITEREG(device_get_parent(dev), phy, + MII_ATH_MMD_DATA, dbg_data); +} + /* * Write half a register */ Modified: head/sys/dev/etherswitch/arswitch/arswitchreg.h ============================================================================== --- head/sys/dev/etherswitch/arswitch/arswitchreg.h Mon Feb 17 01:40:33 2014 (r262009) +++ head/sys/dev/etherswitch/arswitch/arswitchreg.h Mon Feb 17 02:24:58 2014 (r262010) @@ -39,6 +39,8 @@ #define MS(_v, _f) (((_v) & (_f)) >> _f##_S) /* Atheros specific MII registers */ +#define MII_ATH_MMD_ADDR 0x0d +#define MII_ATH_MMD_DATA 0x0e #define MII_ATH_DBG_ADDR 0x1d #define MII_ATH_DBG_DATA 0x1e