From owner-svn-src-head@FreeBSD.ORG Tue Dec 18 23:27:19 2012 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 45ECF7F8; Tue, 18 Dec 2012 23:27:19 +0000 (UTC) (envelope-from jimharris@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id 10E218FC16; Tue, 18 Dec 2012 23:27:19 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.5/8.14.5) with ESMTP id qBINRITU054014; Tue, 18 Dec 2012 23:27:18 GMT (envelope-from jimharris@svn.freebsd.org) Received: (from jimharris@localhost) by svn.freebsd.org (8.14.5/8.14.5/Submit) id qBINRICS054009; Tue, 18 Dec 2012 23:27:18 GMT (envelope-from jimharris@svn.freebsd.org) Message-Id: <201212182327.qBINRICS054009@svn.freebsd.org> From: Jim Harris Date: Tue, 18 Dec 2012 23:27:18 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r244413 - head/sys/dev/nvme X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Dec 2012 23:27:19 -0000 Author: jimharris Date: Tue Dec 18 23:27:18 2012 New Revision: 244413 URL: http://svnweb.freebsd.org/changeset/base/244413 Log: Map BAR 4/5, because NVMe spec says devices may place the MSI-X table behind BAR 4/5, rather than in BAR 0/1 with the control/doorbell registers. Sponsored by: Intel Modified: head/sys/dev/nvme/nvme.c head/sys/dev/nvme/nvme_ctrlr.c head/sys/dev/nvme/nvme_private.h Modified: head/sys/dev/nvme/nvme.c ============================================================================== --- head/sys/dev/nvme/nvme.c Tue Dec 18 22:18:54 2012 (r244412) +++ head/sys/dev/nvme/nvme.c Tue Dec 18 23:27:18 2012 (r244413) @@ -313,6 +313,11 @@ nvme_detach (device_t dev) ctrlr->resource_id, ctrlr->resource); } + if (ctrlr->bar4_resource != NULL) { + bus_release_resource(dev, SYS_RES_MEMORY, + ctrlr->bar4_resource_id, ctrlr->bar4_resource); + } + #ifdef CHATHAM2 if (ctrlr->chatham_resource != NULL) { bus_release_resource(dev, SYS_RES_MEMORY, Modified: head/sys/dev/nvme/nvme_ctrlr.c ============================================================================== --- head/sys/dev/nvme/nvme_ctrlr.c Tue Dec 18 22:18:54 2012 (r244412) +++ head/sys/dev/nvme/nvme_ctrlr.c Tue Dec 18 23:27:18 2012 (r244413) @@ -78,6 +78,17 @@ nvme_ctrlr_allocate_bar(struct nvme_cont ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource); ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle; + /* + * The NVMe spec allows for the MSI-X table to be placed behind + * BAR 4/5, separate from the control/doorbell registers. Always + * try to map this bar, because it must be mapped prior to calling + * pci_alloc_msix(). If the table isn't behind BAR 4/5, + * bus_alloc_resource() will just return NULL which is OK. + */ + ctrlr->bar4_resource_id = PCIR_BAR(4); + ctrlr->bar4_resource = bus_alloc_resource(ctrlr->dev, SYS_RES_MEMORY, + &ctrlr->bar4_resource_id, 0, ~0, 1, RF_ACTIVE); + return (0); } Modified: head/sys/dev/nvme/nvme_private.h ============================================================================== --- head/sys/dev/nvme/nvme_private.h Tue Dec 18 22:18:54 2012 (r244412) +++ head/sys/dev/nvme/nvme_private.h Tue Dec 18 23:27:18 2012 (r244413) @@ -199,6 +199,14 @@ struct nvme_controller { int resource_id; struct resource *resource; + /* + * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, + * separate from the control registers which are in BAR 0/1. These + * members track the mapping of BAR 4/5 for that reason. + */ + int bar4_resource_id; + struct resource *bar4_resource; + #ifdef CHATHAM2 bus_space_tag_t chatham_bus_tag; bus_space_handle_t chatham_bus_handle;