From owner-dev-commits-src-main@freebsd.org Mon May 3 11:39:17 2021 Return-Path: Delivered-To: dev-commits-src-main@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id AA190630091; Mon, 3 May 2021 11:39:17 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4FYgx14Lvmz4k3Y; Mon, 3 May 2021 11:39:17 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 7A3881D85A; Mon, 3 May 2021 11:39:17 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 143BdHCg041376; Mon, 3 May 2021 11:39:17 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 143BdH9u041375; Mon, 3 May 2021 11:39:17 GMT (envelope-from git) Date: Mon, 3 May 2021 11:39:17 GMT Message-Id: <202105031139.143BdH9u041375@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Konstantin Belousov Subject: git: 8f1562430fbb - main - Add Apollo Lake SIO/LPSS UARTs PCI IDs MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: kib X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 8f1562430fbb83f6cedff6450e1aa1b593e3d7e7 Auto-Submitted: auto-generated X-BeenThere: dev-commits-src-main@freebsd.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Commit messages for the main branch of the src repository List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 03 May 2021 11:39:17 -0000 The branch main has been updated by kib: URL: https://cgit.FreeBSD.org/src/commit/?id=8f1562430fbb83f6cedff6450e1aa1b593e3d7e7 commit 8f1562430fbb83f6cedff6450e1aa1b593e3d7e7 Author: Jose Luis Duran AuthorDate: 2021-05-02 21:20:25 +0000 Commit: Konstantin Belousov CommitDate: 2021-05-03 11:38:52 +0000 Add Apollo Lake SIO/LPSS UARTs PCI IDs Add PCI IDs for Intel Apollo Lake Series HSUARTs: # pciconf -ll drv selector class rev hdr vendor device subven subdev uart0@pci0:0:24:0: 118000 0b 00 8086 5abc 8086 7270 uart1@pci0:0:24:1: 118000 0b 00 8086 5abe 8086 7270 uart2@pci0:0:24:2: 118000 0b 00 8086 5ac0 8086 7270 uart3@pci0:0:24:3: 118000 0b 00 8086 5aee 8086 7270 NB (Intel Document Number 336256-004US): 1. The E3900 and A3900 Series Processors support four LPSS_UART ports, while the N- and J- Series Processors support only LPSS_UART [2:1] ports. 2. The LPSS_UART1 port is dedicated for discrete Global Navigation Satellite System (GNSS). This port can be used for generic UART functionality if GNSS is not used. 3. The LPSS_UART2 port is dedicated for host OS debug. 4. The LPSS_UART0 and LPSS_UART3 ports are for generic UART functionality. 5. Only UART [1:0] ports support DMA. PR: 255556 Submitted by: Jose Luis Duran MFC after: 1 week --- sys/dev/uart/uart_bus_pci.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/sys/dev/uart/uart_bus_pci.c b/sys/dev/uart/uart_bus_pci.c index 123ee3e26829..707b82dc078b 100644 --- a/sys/dev/uart/uart_bus_pci.c +++ b/sys/dev/uart/uart_bus_pci.c @@ -147,6 +147,14 @@ static const struct pci_id pci_ns8250_ids[] = { { 0x8086, 0x2e17, 0xffff, 0, "4 Series Chipset Serial KT Controller", 0x10 }, { 0x8086, 0x3b67, 0xffff, 0, "5 Series/3400 Series Chipset KT Controller", 0x10 }, +{ 0x8086, 0x5abc, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 0", 0x10, + 24 * DEFAULT_RCLK, 2 }, +{ 0x8086, 0x5abe, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 1", 0x10, + 24 * DEFAULT_RCLK, 2 }, +{ 0x8086, 0x5ac0, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 2", 0x10, + 24 * DEFAULT_RCLK, 2 }, +{ 0x8086, 0x5aee, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 3", 0x10, + 24 * DEFAULT_RCLK, 2 }, { 0x8086, 0x8811, 0xffff, 0, "Intel EG20T Serial Port 0", 0x10 }, { 0x8086, 0x8812, 0xffff, 0, "Intel EG20T Serial Port 1", 0x10 }, { 0x8086, 0x8813, 0xffff, 0, "Intel EG20T Serial Port 2", 0x10 },