Date: Fri, 9 Jan 1998 19:40:06 +1030 From: Greg Lehey <grog@lemis.com> To: Mike Smith <mike@smith.net.au> Cc: hardware@FreeBSD.ORG Subject: Re: LS-120, Riva 128, ASUS motherboard Message-ID: <19980109194006.42229@lemis.com> In-Reply-To: <199801090814.SAA01031@word.smith.net.au>; from Mike Smith on Fri, Jan 09, 1998 at 06:44:42PM %2B1030 References: <19980109181602.10780@lemis.com> <199801090814.SAA01031@word.smith.net.au>
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On Fri, Jan 09, 1998 at 06:44:42PM +1030, Mike Smith wrote: >> On Fri, Jan 09, 1998 at 05:21:15PM +1030, Mike Smith wrote: >>>> I've seen this claim before from numerous places, but they all refer >>>> to Tom's Hardware Guide. >>> >>> I did? >> >> Indirectly. You didn't name any source that didn't refer directly or >> indirectly to them. > > I mentioned Intel. Do they? No. >>>> I have a TX board (IWill P55XB2) with 96 MB and something on the board >>>> which looks like a tag RAM, but haven't got round to measuring it (or >>>> even finding something I can measure with). >>> >>> What makes it "look like a tag RAM"? >> >> It's long, thin, black, has legs, and is near the cache chips. Sure, >> it could be lots of other things, but I wasn't able to locate the part >> number. > > That sounds like a crossover from the discussion yesterday. Does it > have a coloured stripe? 8) No, it's plain black, and it has more than 8 legs. >>> I would recommend Intel's website and the datasheets for the 430TX >>> chipset. >> >> URL? Yes, I know I'm lazy. But I have other things which I find more >> pressing. > > Scum; Intel have completely rearranged their site; none of my bookmarks > work anymore. > > Try under http://www.intel.com/design/pcisets/datashts Ahh. http://www.intel.com/design/pcisets/datashts/290559.htm. Extract: The Intel 430TX PCIset (430TX) consists of the 82439TX System Controller (MTXC) and the 82371AB PCI ISA IDE Xcelerator (PIIX4). [...] The MTXC integrates the cache and main memory DRAM control functions and provides bus control to transfers between the CPU, cache, main memory, and the PCI Bus. The second level (L2) cache controller supports a writeback cache policy for cache sizes of 256 Kbytes and 512 Kbytes. I'm downloading the document, and will print it out, but this certainly doesn't sound like Tom's Hardware Guide. Greg
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