Date: Thu, 12 Jun 2014 22:32:10 GMT From: op@FreeBSD.org To: svn-soc-all@FreeBSD.org Subject: socsvn commit: r269491 - soc2014/op/freebsd-base/sys/i386/i386 Message-ID: <201406122232.s5CMWADW055259@socsvn.freebsd.org>
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Author: op Date: Thu Jun 12 22:32:09 2014 New Revision: 269491 URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=269491 Log: SMAP i386: identify SMAP on boot git: https://github.com/opntr/opBSD/tree/op/gsoc2014/smap Signed-off-by: Oliver Pinter <oliver.pntr@gmail.com> Modified: soc2014/op/freebsd-base/sys/i386/i386/identcpu.c soc2014/op/freebsd-base/sys/i386/i386/initcpu.c Modified: soc2014/op/freebsd-base/sys/i386/i386/identcpu.c ============================================================================== --- soc2014/op/freebsd-base/sys/i386/i386/identcpu.c Thu Jun 12 22:31:48 2014 (r269490) +++ soc2014/op/freebsd-base/sys/i386/i386/identcpu.c Thu Jun 12 22:32:09 2014 (r269491) @@ -860,6 +860,47 @@ ); } + if (cpu_stdext_feature != 0) { + printf("\n Structured Extended Features=0x%b", + cpu_stdext_feature, + "\020" + /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ + "\001FSGSBASE" + "\002TSCADJ" + /* Bit Manipulation Instructions */ + "\004BMI1" + /* Hardware Lock Elision */ + "\005HLE" + /* Advanced Vector Instructions 2 */ + "\006AVX2" + /* Supervisor Mode Execution Prot. */ + "\010SMEP" + /* Bit Manipulation Instructions */ + "\011BMI2" + "\012ERMS" + /* Invalidate Processor Context ID */ + "\013INVPCID" + /* Restricted Transactional Memory */ + "\014RTM" + /* Intel Memory Protection Extensions */ + "\017MPX" + /* AVX512 Foundation */ + "\021AVX512F" + /* Enhanced NRBG */ + "\023RDSEED" + /* ADCX + ADOX */ + "\024ADX" + /* Supervisor Mode Access Prevention */ + "\025SMAP" + "\030CLFLUSHOPT" + "\032PROCTRACE" + "\033AVX512PF" + "\034AVX512ER" + "\035AVX512CD" + "\036SHA" + ); + } + if (via_feature_rng != 0 || via_feature_xcrypt != 0) print_via_padlock_info(); @@ -1128,6 +1169,25 @@ cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; } + if (cpu_high >= 7) { + cpuid_count(7, 0, regs); + cpu_stdext_feature = regs[1]; + + /* + * Some hypervisors fail to filter out unsupported + * extended features. For now, disable the + * extensions, activation of which requires setting a + * bit in CR4, and which VM monitors do not support. + */ + if (cpu_feature2 & CPUID2_HV) { + cpu_stdext_disable = CPUID_STDEXT_FSGSBASE | + CPUID_STDEXT_SMEP | CPUID_STDEXT_SMAP; + } else + cpu_stdext_disable = 0; + TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); + cpu_stdext_feature &= ~cpu_stdext_disable; + } + /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */ if (cpu_vendor_id == CPU_VENDOR_INTEL || cpu_vendor_id == CPU_VENDOR_AMD) { Modified: soc2014/op/freebsd-base/sys/i386/i386/initcpu.c ============================================================================== --- soc2014/op/freebsd-base/sys/i386/i386/initcpu.c Thu Jun 12 22:31:48 2014 (r269490) +++ soc2014/op/freebsd-base/sys/i386/i386/initcpu.c Thu Jun 12 22:32:09 2014 (r269491) @@ -97,6 +97,7 @@ char cpu_vendor[20] = ""; /* CPU Origin code */ u_int cpu_vendor_id = 0; /* CPU vendor ID */ u_int cpu_clflush_line_size = 32; +u_int cpu_stdext_feature; u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
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