Date: Sun, 2 Feb 1997 18:34:37 -0500 From: "David S. Miller" <davem@jenolan.rutgers.edu> To: terry@lambert.org Cc: smp@csn.net, terry@lambert.org, michaelh@cet.co.jp, netdev@roxanne.nuclecu.unam.mx, roque@di.fc.ul.pt, freebsd-smp@FreeBSD.org, smpdev@roxanne.nuclecu.unam.mx Subject: Re: SMP Message-ID: <199702022334.SAA19878@jenolan.caipgeneral> In-Reply-To: <199702022325.QAA09083@phaeton.artisoft.com> (message from Terry Lambert on Sun, 2 Feb 1997 16:25:26 -0700 (MST))
next in thread | previous in thread | raw e-mail | index | archive | help
From: Terry Lambert <terry@lambert.org> Date: Sun, 2 Feb 1997 16:25:26 -0700 (MST) What do you have to say about treating the cache line coherency? Is it necessary, or is it automatic? I'm curious about Alan's theory about the situation as well. But on the whole, if a machine cannot pass the simple test you have described here, and there is no side explanation for it, chuck the machine because it is surely broken. If you start trying to code for such behavior, it will be more trouble than it's worth. Claim it broken hardware and be done with it, ahhh life is sweet again ;-) But I think this will be explained away by something else, I can't let myself believe that Intel would mess something so basic and necessary like this these days. ---------------------------------------------//// Yow! 11.26 MB/s remote host TCP bandwidth & //// 199 usec remote TCP latency over 100Mb/s //// ethernet. Beat that! //// -----------------------------------------////__________ o David S. Miller, davem@caip.rutgers.edu /_____________/ / // /_/ ><
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?199702022334.SAA19878>