From owner-svn-src-stable-7@FreeBSD.ORG Mon Feb 9 01:26:32 2009 Return-Path: Delivered-To: svn-src-stable-7@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 025F31065670; Mon, 9 Feb 2009 01:26:32 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id DACF98FC14; Mon, 9 Feb 2009 01:26:31 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n191QVuW040545; Mon, 9 Feb 2009 01:26:31 GMT (envelope-from yongari@svn.freebsd.org) Received: (from yongari@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n191QVjF040543; Mon, 9 Feb 2009 01:26:31 GMT (envelope-from yongari@svn.freebsd.org) Message-Id: <200902090126.n191QVjF040543@svn.freebsd.org> From: Pyun YongHyeon Date: Mon, 9 Feb 2009 01:26:31 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-7@freebsd.org X-SVN-Group: stable-7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r188357 - in stable/7/sys: . contrib/pf dev/cxgb dev/re pci X-BeenThere: svn-src-stable-7@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for only the 7-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Feb 2009 01:26:32 -0000 Author: yongari Date: Mon Feb 9 01:26:31 2009 New Revision: 188357 URL: http://svn.freebsd.org/changeset/base/188357 Log: MFC: r185897,185900-185901,185903 r185897: Always put controller into known state before device intialization. While here remove re_reset calls invoked in system error case as controller reset is always done in device initialization. r185900: Newer RealTek controllers requires setting stop request bit to terminate active Tx/Rx operation. r185901: Don't access undocumented register 0x82 on controllers that have no such register. While here clear undocumented PHY register 0x0B for RTL8110S. r185903: Make WOL work on RTL8168B. This controller seems to require explicit command to enable Rx MAC prior to entering D3. Modified: stable/7/sys/ (props changed) stable/7/sys/contrib/pf/ (props changed) stable/7/sys/dev/cxgb/ (props changed) stable/7/sys/dev/re/if_re.c stable/7/sys/pci/if_rlreg.h Modified: stable/7/sys/dev/re/if_re.c ============================================================================== --- stable/7/sys/dev/re/if_re.c Mon Feb 9 01:16:36 2009 (r188356) +++ stable/7/sys/dev/re/if_re.c Mon Feb 9 01:26:31 2009 (r188357) @@ -700,7 +700,12 @@ re_reset(struct rl_softc *sc) if (i == RL_TIMEOUT) device_printf(sc->rl_dev, "reset never completed!\n"); - CSR_WRITE_1(sc, 0x82, 1); + if ((sc->rl_flags & RL_FLAG_PHY8169) != 0) + CSR_WRITE_1(sc, 0x82, 1); + if ((sc->rl_flags & RL_FLAG_PHY8110S) != 0) { + CSR_WRITE_1(sc, 0x82, 1); + re_gmii_writereg(sc->rl_dev, 1, 0x0B, 0); + } } #ifdef RE_DIAG @@ -756,7 +761,6 @@ re_diag(struct rl_softc *sc) ifp->if_flags |= IFF_PROMISC; sc->rl_testmode = 1; - re_reset(sc); re_init_locked(sc); sc->rl_flags |= RL_FLAG_LINK; if (sc->rl_type == RL_8169) @@ -1236,6 +1240,9 @@ re_attach(device_t dev) case RL_HWREV_8139CPLUS: sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER; break; + case RL_HWREV_8110S: + sc->rl_flags |= RL_FLAG_PHY8110S; + break; case RL_HWREV_8100E: case RL_HWREV_8101E: sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR | @@ -1245,10 +1252,12 @@ re_attach(device_t dev) case RL_HWREV_8102EL: sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | - RL_FLAG_MACSTAT | RL_FLAG_FASTETHER; + RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP; break; case RL_HWREV_8168_SPIN1: case RL_HWREV_8168_SPIN2: + sc->rl_flags |= RL_FLAG_WOLRXENB; + /* FALLTHROUGH */ case RL_HWREV_8168_SPIN3: sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; @@ -1258,7 +1267,8 @@ re_attach(device_t dev) case RL_HWREV_8168CP: case RL_HWREV_8168D: sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | - RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT; + RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | + RL_FLAG_CMDSTOP; /* * These controllers support jumbo frame but it seems * that enabling it requires touching additional magic @@ -1271,10 +1281,14 @@ re_attach(device_t dev) */ sc->rl_flags |= RL_FLAG_NOJUMBO; break; + case RL_HWREV_8169: + case RL_HWREV_8169S: + sc->rl_flags |= RL_FLAG_PHY8169; + break; case RL_HWREV_8169_8110SB: case RL_HWREV_8169_8110SC: case RL_HWREV_8169_8110SBL: - sc->rl_flags |= RL_FLAG_PHYWAKE; + sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHY8169; break; default: break; @@ -2091,10 +2105,8 @@ re_poll_locked(struct ifnet *ifp, enum p * XXX check behaviour on receiver stalls. */ - if (status & RL_ISR_SYSTEM_ERR) { - re_reset(sc); + if (status & RL_ISR_SYSTEM_ERR) re_init_locked(sc); - } } } #endif /* DEVICE_POLLING */ @@ -2158,10 +2170,8 @@ re_int_task(void *arg, int npending) RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) re_txeof(sc); - if (status & RL_ISR_SYSTEM_ERR) { - re_reset(sc); + if (status & RL_ISR_SYSTEM_ERR) re_init_locked(sc); - } if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); @@ -2482,6 +2492,9 @@ re_init_locked(struct rl_softc *sc) */ re_stop(sc); + /* Put controller into known state. */ + re_reset(sc); + /* * Enable C+ RX and TX mode, as well as VLAN stripping and * RX checksum offload. We must configure the C+ register @@ -2870,7 +2883,12 @@ re_stop(struct rl_softc *sc) callout_stop(&sc->rl_stat_callout); ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); - CSR_WRITE_1(sc, RL_COMMAND, 0x00); + if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) + CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | + RL_CMD_RX_ENB); + else + CSR_WRITE_1(sc, RL_COMMAND, 0x00); + DELAY(1000); CSR_WRITE_2(sc, RL_IMR, 0x0000); CSR_WRITE_2(sc, RL_ISR, 0xFFFF); @@ -3000,6 +3018,9 @@ re_setwol(struct rl_softc *sc) return; ifp = sc->rl_ifp; + if ((ifp->if_capenable & IFCAP_WOL) != 0 && + (sc->rl_flags & RL_FLAG_WOLRXENB) != 0) + CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); /* Enable config register write. */ CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); Modified: stable/7/sys/pci/if_rlreg.h ============================================================================== --- stable/7/sys/pci/if_rlreg.h Mon Feb 9 01:16:36 2009 (r188356) +++ stable/7/sys/pci/if_rlreg.h Mon Feb 9 01:26:31 2009 (r188357) @@ -308,6 +308,7 @@ #define RL_CMD_TX_ENB 0x0004 #define RL_CMD_RX_ENB 0x0008 #define RL_CMD_RESET 0x0010 +#define RL_CMD_STOPREQ 0x0080 /* * EEPROM control register @@ -856,6 +857,10 @@ struct rl_softc { #define RL_FLAG_DESCV2 0x0040 #define RL_FLAG_MACSTAT 0x0080 #define RL_FLAG_FASTETHER 0x0100 +#define RL_FLAG_CMDSTOP 0x0200 +#define RL_FLAG_PHY8169 0x0400 +#define RL_FLAG_PHY8110S 0x0800 +#define RL_FLAG_WOLRXENB 0x1000 #define RL_FLAG_LINK 0x8000 };