From owner-svn-src-head@FreeBSD.ORG Sun Mar 16 20:39:39 2014 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id B0CDFDC9; Sun, 16 Mar 2014 20:39:39 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 9E891110; Sun, 16 Mar 2014 20:39:39 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s2GKddu5051325; Sun, 16 Mar 2014 20:39:39 GMT (envelope-from ian@svn.freebsd.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s2GKdd4A051324; Sun, 16 Mar 2014 20:39:39 GMT (envelope-from ian@svn.freebsd.org) Message-Id: <201403162039.s2GKdd4A051324@svn.freebsd.org> From: Ian Lepore Date: Sun, 16 Mar 2014 20:39:39 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r263251 - head/sys/arm/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 16 Mar 2014 20:39:39 -0000 Author: ian Date: Sun Mar 16 20:39:39 2014 New Revision: 263251 URL: http://svnweb.freebsd.org/changeset/base/263251 Log: Use armv7 TLB flush code, not arm11, for cortex-a processors. The armv7 architecture uses a unified TLB model for maintenence ops even if separate instruction and data TLBs are implemented in hardware. That means that there's no distinction between the 'I' and 'D' flavors of flush, they all use the same 'ID' implementation. On the other hand, there is a difference between SMP and UP on armv7, but not on arm11, so use the armv7 routines for cortex-a processors. Modified: head/sys/arm/arm/cpufunc.c Modified: head/sys/arm/arm/cpufunc.c ============================================================================== --- head/sys/arm/arm/cpufunc.c Sun Mar 16 20:34:45 2014 (r263250) +++ head/sys/arm/arm/cpufunc.c Sun Mar 16 20:39:39 2014 (r263251) @@ -754,14 +754,18 @@ struct cpu_functions cortexa_cpufuncs = cpufunc_faultstatus, /* Faultstatus */ cpufunc_faultaddress, /* Faultaddress */ - /* TLB functions */ + /* + * TLB functions. ARMv7 does all TLB ops based on a unified TLB model + * whether the hardware implements separate I+D or not, so we use the + * same 'ID' functions for all 3 variations. + */ armv7_tlb_flushID, /* tlb_flushID */ armv7_tlb_flushID_SE, /* tlb_flushID_SE */ - arm11_tlb_flushI, /* tlb_flushI */ - arm11_tlb_flushI_SE, /* tlb_flushI_SE */ - arm11_tlb_flushD, /* tlb_flushD */ - arm11_tlb_flushD_SE, /* tlb_flushD_SE */ + armv7_tlb_flushID, /* tlb_flushI */ + armv7_tlb_flushID_SE, /* tlb_flushI_SE */ + armv7_tlb_flushID, /* tlb_flushD */ + armv7_tlb_flushID_SE, /* tlb_flushD_SE */ /* Cache operations */