From owner-freebsd-hackers@FreeBSD.ORG Sat Oct 11 01:27:24 2003 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 800A616A4B3 for ; Sat, 11 Oct 2003 01:27:24 -0700 (PDT) Received: from arginine.spc.org (arginine.spc.org [195.206.69.236]) by mx1.FreeBSD.org (Postfix) with ESMTP id 6468543F93 for ; Sat, 11 Oct 2003 01:27:21 -0700 (PDT) (envelope-from bms@spc.org) Received: from localhost (localhost [127.0.0.1]) by arginine.spc.org (Postfix) with ESMTP id 9B981654BB; Sat, 11 Oct 2003 09:27:20 +0100 (BST) Received: from arginine.spc.org ([127.0.0.1]) by localhost (arginine.spc.org [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 90690-04-2; Sat, 11 Oct 2003 09:27:20 +0100 (BST) Received: from saboteur.dek.spc.org (lardystuffer.demon.co.uk [212.228.40.202]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by arginine.spc.org (Postfix) with ESMTP id 34A07654B5; Sat, 11 Oct 2003 09:27:19 +0100 (BST) Received: by saboteur.dek.spc.org (Postfix, from userid 1001) id 441FF35; Sat, 11 Oct 2003 09:27:11 +0100 (BST) Date: Sat, 11 Oct 2003 09:27:11 +0100 From: Bruce M Simpson To: Peter Jeremy Message-ID: <20031011082711.GB679@saboteur.dek.spc.org> Mail-Followup-To: Peter Jeremy , Andrew Gallatin , Bruce M Simpson , freebsd-hackers@freebsd.org References: <20031010103640.6F5A216A4BF@hub.freebsd.org> <20031010134400.GE803@saboteur.dek.spc.org> <16263.1019.939450.708832@grasshopper.cs.duke.edu> <20031011035827.GD75796@server.c211-28-27-130.belrs2.nsw.optusnet.com.au> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20031011035827.GD75796@server.c211-28-27-130.belrs2.nsw.optusnet.com.au> cc: Andrew Gallatin cc: freebsd-hackers@freebsd.org Subject: Re: Determining CPU features / cache organization from userland X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 11 Oct 2003 08:27:24 -0000 X-List-Received-Date: Sat, 11 Oct 2003 08:27:24 -0000 On Sat, Oct 11, 2003 at 01:58:27PM +1000, Peter Jeremy wrote: > >If you do this, it may make sense to use the same names as MacOSX. > > What if your hardware has different linesizes for different caches? I noticed whilst peering in Apple Developer Notes that G5 has 128 byte cache line size, and this screws up mutexes bigtime. (!!) OS X definitions considered too PowerPC centric. I think the best way to handle all cases is thus:- - Support 3 levels of cache. - Each level may be unified or split between code and data not-quite-Von-Neumann-style. - Allow explicit retrieval of this info keyed on the cache you're interested in. This means: hw.cache.lN.(linesize|lines|sets) - Do similar for the TLB insofar as we can return information about the chip's TLB. I know for example from talking to peter@ that the Opteron is quite a different beast (ASNs, flush filter, etc). - Assume that all CPUs have identical characteristics in an SMP system. Trying to assume otherwise is pointless. People should be using matched chips anyway. BMS