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Date:      Fri, 6 Jan 2012 21:43:26 +0000 (UTC)
From:      Pyun YongHyeon <yongari@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-9@freebsd.org
Subject:   svn commit: r229736 - stable/9/sys/dev/et
Message-ID:  <201201062143.q06LhQDm009532@svn.freebsd.org>

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Author: yongari
Date: Fri Jan  6 21:43:26 2012
New Revision: 229736
URL: http://svn.freebsd.org/changeset/base/229736

Log:
  MFC r228333,228335-228336,228362,228368-228369,228381:
  r228333:
    Protect SIOCSIFMTU ioctl handler with driver lock.
    Don't blindly re-initialize controller whenever MTU is changed.
    Now, reinitializing is done only when driver is running.
  
    While here, remove unnecessary assignment of error value since it
    was already initialized to 0.
  
  r228335:
    Consistently use a tab character instead of using either a space or
    tab after #define.
    While I'm here consistently use capital letters when it uses
    hexadecimal notation.
  
    No functional changes.
  
  r228336:
    Disable all clocks and put PHY into COMA before entering into
    suspend state.  This will save more power.
    On resume, make sure to enable all clocks.  While I'm here, if
    controller is not fast ethernet, enable gigabit PHY.
  
  r228362:
    Do not disable interrupt without knowing whether the raised
    interrupt is ours.  Note, interrupts are automatically ACKed when
    the status register is read.
    Add RX/TX DMA error to interrupt handler and do full controller
    reset if driver happen to encounter these errors.  There is no way
    to recover from these DMA errors without controller reset.
    Rename local variable name intrs with status to enhance
    readability.
  
    While I'm here, rename ET_INTR_TXEOF and ET_INTR_RXEOF to
    ET_INTR_TXDMA and ET_INTR_RXDMA respectively.  These interrupts
    indicate that a frame is successfully DMAed to controller's
    internal FIFO and they have nothing to do with EOF(end of frame).
    Driver does not need to wait actual end of TX/RX of a frame(e.g.
    no need to wait the end signal of TX which is generated when a
    frame in TX FIFO is emptied by MAC).  Previous names were somewhat
    confusing.
  
  r228368:
    Remove unnecessary definition of ET_PCIR_BAR.  Controller support
    I/O memory only.
    While here, use pci_set_max_read_req(9) rather than directly
    manipulating PCIe device control register.
  
  r228369:
    Announce flow control ability to PHY driver and enable RX flow
    control.  Controller does not automatically generate pause frames
    based on number of available RX buffers so it's very hard to
    know when driver should generate XON frame in time.  The only
    mechanism driver can detect low number of RX buffer condition is
    ET_INTR_RXRING0_LOW or ET_INTR_RXRING1_LOW interrupt.  This
    interrupt is generated whenever controller notices the number of
    available RX buffers are lower than pre-programmed value(
    ET_RX_RING0_MINCNT and ET_RX_RING1_MINCNT register).  This scheme
    does not provide a way to detect when controller sees enough number
    of RX buffers again such that efficient generation of XON/XOFF
    frame is not easy.
  
    While here, add more flow control related register definition.
  
  r228381:
    FreeBSD driver does not require arpcom structure in softc.

Modified:
  stable/9/sys/dev/et/if_et.c
  stable/9/sys/dev/et/if_etreg.h
  stable/9/sys/dev/et/if_etvar.h
Directory Properties:
  stable/9/sys/   (props changed)
  stable/9/sys/amd64/include/xen/   (props changed)
  stable/9/sys/boot/   (props changed)
  stable/9/sys/boot/i386/efi/   (props changed)
  stable/9/sys/boot/ia64/efi/   (props changed)
  stable/9/sys/boot/ia64/ski/   (props changed)
  stable/9/sys/boot/powerpc/boot1.chrp/   (props changed)
  stable/9/sys/boot/powerpc/ofw/   (props changed)
  stable/9/sys/cddl/contrib/opensolaris/   (props changed)
  stable/9/sys/conf/   (props changed)
  stable/9/sys/contrib/dev/acpica/   (props changed)
  stable/9/sys/contrib/octeon-sdk/   (props changed)
  stable/9/sys/contrib/pf/   (props changed)
  stable/9/sys/contrib/x86emu/   (props changed)

Modified: stable/9/sys/dev/et/if_et.c
==============================================================================
--- stable/9/sys/dev/et/if_et.c	Fri Jan  6 21:28:29 2012	(r229735)
+++ stable/9/sys/dev/et/if_et.c	Fri Jan  6 21:43:26 2012	(r229736)
@@ -220,6 +220,7 @@ et_attach(device_t dev)
 	struct et_softc *sc;
 	struct ifnet *ifp;
 	uint8_t eaddr[ETHER_ADDR_LEN];
+	uint32_t pmcfg;
 	int cap, error, msic;
 
 	sc = device_get_softc(dev);
@@ -249,9 +250,9 @@ et_attach(device_t dev)
 	/*
 	 * Allocate IO memory
 	 */
-	sc->sc_mem_rid = ET_PCIR_BAR;
+	sc->sc_mem_rid = PCIR_BAR(0);
 	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
-						&sc->sc_mem_rid, RF_ACTIVE);
+	    &sc->sc_mem_rid, RF_ACTIVE);
 	if (sc->sc_mem_res == NULL) {
 		device_printf(dev, "can't allocate IO memory\n");
 		return (ENXIO);
@@ -304,8 +305,11 @@ et_attach(device_t dev)
 
 	et_get_eaddr(dev, eaddr);
 
-	CSR_WRITE_4(sc, ET_PM,
-		    ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE);
+	/* Take PHY out of COMA and enable clocks. */
+	pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE;
+	if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0)
+		pmcfg |= EM_PM_GIGEPHY_ENB;
+	CSR_WRITE_4(sc, ET_PM, pmcfg);
 
 	et_reset(sc);
 
@@ -328,7 +332,8 @@ et_attach(device_t dev)
 	et_chip_attach(sc);
 
 	error = mii_attach(dev, &sc->sc_miibus, ifp, et_ifmedia_upd,
-	    et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
+	    et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
+	    MIIF_DOPAUSE);
 	if (error) {
 		device_printf(dev, "attaching PHYs failed\n");
 		goto fail;
@@ -544,12 +549,23 @@ et_miibus_statchg(device_t dev)
 
 	if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
 		cfg2 |= ET_MAC_CFG2_FDX;
+		/*
+		 * Controller lacks automatic TX pause frame
+		 * generation so it should be handled by driver.
+		 * Even though driver can send pause frame with
+		 * arbitrary pause time, controller does not
+		 * provide a way that tells how many free RX
+		 * buffers are available in controller.  This
+		 * limitation makes it hard to generate XON frame
+		 * in time on driver side so don't enable TX flow
+		 * control.
+		 */
 #ifdef notyet
 		if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE)
 			cfg1 |= ET_MAC_CFG1_TXFLOW;
+#endif
 		if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE)
 			cfg1 |= ET_MAC_CFG1_RXFLOW;
-#endif
 	} else
 		ctrl |= ET_MAC_CTRL_GHDX;
 
@@ -718,12 +734,7 @@ et_bus_config(struct et_softc *sc)
 	/*
 	 * Set max read request size to 2048 bytes
 	 */
-	val = pci_read_config(sc->dev,
-	    sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
-	val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
-	val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K;
-	pci_write_config(sc->dev,
-	    sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, val, 2);
+	pci_set_max_read_req(sc->dev, 2048);
 
 	return (0);
 }
@@ -1154,34 +1165,40 @@ et_intr(void *xsc)
 {
 	struct et_softc *sc = xsc;
 	struct ifnet *ifp;
-	uint32_t intrs;
+	uint32_t status;
 
 	ET_LOCK(sc);
 	ifp = sc->ifp;
-	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
-		ET_UNLOCK(sc);
-		return;
-	}
+	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
+		goto done;
+
+	status = CSR_READ_4(sc, ET_INTR_STATUS);
+	if ((status & ET_INTRS) == 0)
+		goto done;
 
 	/* Disable further interrupts. */
 	CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff);
 
-	intrs = CSR_READ_4(sc, ET_INTR_STATUS);
-	if ((intrs & ET_INTRS) == 0)
-		goto done;
-
-	if (intrs & ET_INTR_RXEOF)
+	if (status & (ET_INTR_RXDMA_ERROR | ET_INTR_TXDMA_ERROR)) {
+		device_printf(sc->dev, "DMA error(0x%08x) -- resetting\n",
+		    status);
+		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+		et_init_locked(sc);
+		ET_UNLOCK(sc);
+		return;
+	}
+	if (status & ET_INTR_RXDMA)
 		et_rxeof(sc);
-	if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER))
+	if (status & (ET_INTR_TXDMA | ET_INTR_TIMER))
 		et_txeof(sc);
-	if (intrs & ET_INTR_TIMER)
+	if (status & ET_INTR_TIMER)
 		CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer);
-done:
 	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 		CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS);
 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 			et_start_locked(ifp);
 	}
+done:
 	ET_UNLOCK(sc);
 }
 
@@ -1287,11 +1304,11 @@ et_ioctl(struct ifnet *ifp, u_long cmd, 
 			ET_LOCK(sc);
 			et_setmulti(sc);
 			ET_UNLOCK(sc);
-			error = 0;
 		}
 		break;
 
 	case SIOCSIFMTU:
+		ET_LOCK(sc);
 #if 0
 		if (sc->sc_flags & ET_FLAG_JUMBO)
 			max_framelen = ET_JUMBO_FRAMELEN;
@@ -1301,14 +1318,18 @@ et_ioctl(struct ifnet *ifp, u_long cmd, 
 
 		if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) {
 			error = EOPNOTSUPP;
+			ET_UNLOCK(sc);
 			break;
 		}
 
 		if (ifp->if_mtu != ifr->ifr_mtu) {
 			ifp->if_mtu = ifr->ifr_mtu;
-			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
-			et_init(sc);
+			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+				et_init_locked(sc);
+			}
 		}
+		ET_UNLOCK(sc);
 		break;
 
 	case SIOCSIFCAP:
@@ -1940,8 +1961,12 @@ et_init_txmac(struct et_softc *sc)
 	/* Disable TX MAC and FC(?) */
 	CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE);
 
-	/* No flow control yet */
-	CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0);
+	/*
+	 * Initialize pause time.
+	 * This register should be set before XON/XOFF frame is
+	 * sent by driver.
+	 */
+	CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0 << ET_TXMAC_FLOWCTRL_CFPT_SHIFT);
 
 	/* Enable TX MAC but leave FC(?) diabled */
 	CSR_WRITE_4(sc, ET_TXMAC_CTRL,
@@ -2632,11 +2657,18 @@ static int
 et_suspend(device_t dev)
 {
 	struct et_softc *sc;
+	uint32_t pmcfg;
 
 	sc = device_get_softc(dev);
 	ET_LOCK(sc);
 	if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
 		et_stop(sc);
+	/* Diable all clocks and put PHY into COMA. */
+	pmcfg = CSR_READ_4(sc, ET_PM);
+	pmcfg &= ~(EM_PM_GIGEPHY_ENB | ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE |
+	    ET_PM_RXCLK_GATE);
+	pmcfg |= ET_PM_PHY_SW_COMA;
+	CSR_WRITE_4(sc, ET_PM, pmcfg);
 	ET_UNLOCK(sc);
 	return (0);
 }
@@ -2645,9 +2677,15 @@ static int
 et_resume(device_t dev)
 {
 	struct et_softc *sc;
+	uint32_t pmcfg;
 
 	sc = device_get_softc(dev);
 	ET_LOCK(sc);
+	/* Take PHY out of COMA and enable clocks. */
+	pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE;
+	if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0)
+		pmcfg |= EM_PM_GIGEPHY_ENB;
+	CSR_WRITE_4(sc, ET_PM, pmcfg);
 	if ((sc->ifp->if_flags & IFF_UP) != 0)
 		et_init_locked(sc);
 	ET_UNLOCK(sc);

Modified: stable/9/sys/dev/et/if_etreg.h
==============================================================================
--- stable/9/sys/dev/et/if_etreg.h	Fri Jan  6 21:28:29 2012	(r229735)
+++ stable/9/sys/dev/et/if_etreg.h	Fri Jan  6 21:43:26 2012	(r229736)
@@ -38,11 +38,11 @@
 #ifndef _IF_ETREG_H
 #define _IF_ETREG_H
 
-#define ET_MEM_TXSIZE_EX		182
-#define ET_MEM_RXSIZE_MIN		608
-#define ET_MEM_RXSIZE_DEFAULT		11216
-#define ET_MEM_SIZE			16384
-#define ET_MEM_UNIT			16
+#define	ET_MEM_TXSIZE_EX		182
+#define	ET_MEM_RXSIZE_MIN		608
+#define	ET_MEM_RXSIZE_DEFAULT		11216
+#define	ET_MEM_SIZE			16384
+#define	ET_MEM_UNIT			16
 
 /*
  * PCI registers
@@ -53,270 +53,277 @@
  * ET_PCIV_REPLAY_TIMER_{128,256} are from
  * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-4
  */
-#define ET_PCIR_BAR			PCIR_BAR(0)
+#define	ET_PCIR_DEVICE_CAPS		0x4C
+#define	ET_PCIM_DEVICE_CAPS_MAX_PLSZ	0x7	/* Max playload size */
+#define	ET_PCIV_DEVICE_CAPS_PLSZ_128	0x0
+#define	ET_PCIV_DEVICE_CAPS_PLSZ_256	0x1
+
+#define	ET_PCIR_DEVICE_CTRL		0x50
+#define	ET_PCIM_DEVICE_CTRL_MAX_RRSZ	0x7000	/* Max read request size */
+#define	ET_PCIV_DEVICE_CTRL_RRSZ_2K	0x4000
+
+#define	ET_PCIR_MAC_ADDR0		0xA4
+#define	ET_PCIR_MAC_ADDR1		0xA8
+
+#define	ET_PCIR_EEPROM_STATUS		0xB2	/* XXX undocumented */
+#define	ET_PCIM_EEPROM_STATUS_ERROR	0x4C
+
+#define	ET_PCIR_ACK_LATENCY		0xC0
+#define	ET_PCIV_ACK_LATENCY_128		237
+#define	ET_PCIV_ACK_LATENCY_256		416
+
+#define	ET_PCIR_REPLAY_TIMER		0xC2
+#define	ET_REPLAY_TIMER_RX_L0S_ADJ	250	/* XXX infered from default */
+#define	ET_PCIV_REPLAY_TIMER_128	(711 + ET_REPLAY_TIMER_RX_L0S_ADJ)
+#define	ET_PCIV_REPLAY_TIMER_256	(1248 + ET_REPLAY_TIMER_RX_L0S_ADJ)
 
-#define ET_PCIR_DEVICE_CAPS		0x4c
-#define ET_PCIM_DEVICE_CAPS_MAX_PLSZ	0x7	/* Max playload size */
-#define ET_PCIV_DEVICE_CAPS_PLSZ_128	0x0
-#define ET_PCIV_DEVICE_CAPS_PLSZ_256	0x1
-
-#define ET_PCIR_DEVICE_CTRL		0x50
-#define ET_PCIM_DEVICE_CTRL_MAX_RRSZ	0x7000	/* Max read request size */
-#define ET_PCIV_DEVICE_CTRL_RRSZ_2K	0x4000
-
-#define ET_PCIR_MAC_ADDR0		0xa4
-#define ET_PCIR_MAC_ADDR1		0xa8
-
-#define ET_PCIR_EEPROM_STATUS		0xb2	/* XXX undocumented */
-#define ET_PCIM_EEPROM_STATUS_ERROR	0x4c
-
-#define ET_PCIR_ACK_LATENCY		0xc0
-#define ET_PCIV_ACK_LATENCY_128		237
-#define ET_PCIV_ACK_LATENCY_256		416
-
-#define ET_PCIR_REPLAY_TIMER		0xc2
-#define ET_REPLAY_TIMER_RX_L0S_ADJ	250	/* XXX infered from default */
-#define ET_PCIV_REPLAY_TIMER_128	(711 + ET_REPLAY_TIMER_RX_L0S_ADJ)
-#define ET_PCIV_REPLAY_TIMER_256	(1248 + ET_REPLAY_TIMER_RX_L0S_ADJ)
-
-#define ET_PCIR_L0S_L1_LATENCY		0xcf
+#define	ET_PCIR_L0S_L1_LATENCY		0xCF
 
 /*
  * CSR
  */
-#define ET_TXQUEUE_START		0x0000
-#define ET_TXQUEUE_END			0x0004
-#define ET_RXQUEUE_START		0x0008
-#define ET_RXQUEUE_END			0x000c
-#define ET_QUEUE_ADDR(addr)		(((addr) / ET_MEM_UNIT) - 1)
-#define ET_QUEUE_ADDR_START		0
-#define ET_QUEUE_ADDR_END		ET_QUEUE_ADDR(ET_MEM_SIZE)
-
-#define ET_PM				0x0010
-#define ET_PM_SYSCLK_GATE		0x00000008
-#define ET_PM_TXCLK_GATE		0x00000010
-#define ET_PM_RXCLK_GATE		0x00000020
-
-#define ET_INTR_STATUS			0x0018
-#define ET_INTR_MASK			0x001c
-
-#define ET_SWRST			0x0028
-#define ET_SWRST_TXDMA			0x00000001
-#define ET_SWRST_RXDMA			0x00000002
-#define ET_SWRST_TXMAC			0x00000004
-#define ET_SWRST_RXMAC			0x00000008
-#define ET_SWRST_MAC			0x00000010
-#define ET_SWRST_MAC_STAT		0x00000020
-#define ET_SWRST_MMC			0x00000040
-#define ET_SWRST_SELFCLR_DISABLE	0x80000000
-
-#define ET_MSI_CFG			0x0030
-
-#define ET_LOOPBACK			0x0034
-
-#define ET_TIMER			0x0038
-
-#define ET_TXDMA_CTRL			0x1000
-#define ET_TXDMA_CTRL_HALT		0x00000001
-#define ET_TXDMA_CTRL_CACHE_THR_MASK	0x000000F0
-#define ET_TXDMA_CTRL_SINGLE_EPKT	0x00000100	/* ??? */
-
-#define ET_TX_RING_HI			0x1004
-#define ET_TX_RING_LO			0x1008
-#define ET_TX_RING_CNT			0x100c
-
-#define ET_TX_STATUS_HI			0x101c
-#define ET_TX_STATUS_LO			0x1020
-
-#define ET_TX_READY_POS			0x1024
-#define ET_TX_READY_POS_INDEX_MASK	0x000003FF
-#define ET_TX_READY_POS_WRAP		0x00000400
-
-#define ET_TX_DONE_POS			0x1060
-#define ET_TX_DONE_POS_INDEX_MASK	0x0000003FF
-#define ET_TX_DONE_POS_WRAP		0x000000400
-
-#define ET_RXDMA_CTRL			0x2000
-#define ET_RXDMA_CTRL_HALT		0x00000001
-#define ET_RXDMA_CTRL_RING0_SIZE_MASK	0x00000300
-#define ET_RXDMA_CTRL_RING0_128		0x00000000	/* 127 */
-#define ET_RXDMA_CTRL_RING0_256		0x00000100	/* 255 */
-#define ET_RXDMA_CTRL_RING0_512		0x00000200	/* 511 */
-#define ET_RXDMA_CTRL_RING0_1024	0x00000300	/* 1023 */
-#define ET_RXDMA_CTRL_RING0_ENABLE	0x00000400
-#define ET_RXDMA_CTRL_RING1_SIZE_MASK	0x00001800
-#define ET_RXDMA_CTRL_RING1_2048	0x00000000	/* 2047 */
-#define ET_RXDMA_CTRL_RING1_4096	0x00000800	/* 4095 */
-#define ET_RXDMA_CTRL_RING1_8192	0x00001000	/* 8191 */
-#define ET_RXDMA_CTRL_RING1_16384	0x00001800	/* 16383 (9022?) */
-#define ET_RXDMA_CTRL_RING1_ENABLE	0x00002000
-#define ET_RXDMA_CTRL_HALTED		0x00020000
-
-#define ET_RX_STATUS_LO			0x2004
-#define ET_RX_STATUS_HI			0x2008
-
-#define ET_RX_INTR_NPKTS		0x200c
-#define ET_RX_INTR_DELAY		0x2010
-
-#define ET_RXSTAT_LO			0x2020
-#define ET_RXSTAT_HI			0x2024
-#define ET_RXSTAT_CNT			0x2028
-
-#define ET_RXSTAT_POS			0x2030
-#define ET_RXSTAT_POS_INDEX_MASK	0x00000FFF
-#define ET_RXSTAT_POS_WRAP		0x00001000
-
-#define ET_RXSTAT_MINCNT		0x2038
-
-#define ET_RX_RING0_LO			0x203c
-#define ET_RX_RING0_HI			0x2040
-#define ET_RX_RING0_CNT			0x2044
-
-#define ET_RX_RING0_POS			0x204c
-#define ET_RX_RING0_POS_INDEX_MASK	0x000003FF
-#define ET_RX_RING0_POS_WRAP		0x00000400
-
-#define ET_RX_RING0_MINCNT		0x2054
-
-#define ET_RX_RING1_LO			0x2058
-#define ET_RX_RING1_HI			0x205c
-#define ET_RX_RING1_CNT			0x2060
-
-#define ET_RX_RING1_POS			0x2068
-#define ET_RX_RING1_POS_INDEX		0x000003FF
-#define ET_RX_RING1_POS_WRAP		0x00000400
-
-#define ET_RX_RING1_MINCNT		0x2070
-
-#define ET_TXMAC_CTRL			0x3000
-#define ET_TXMAC_CTRL_ENABLE		0x00000001
-#define ET_TXMAC_CTRL_FC_DISABLE	0x00000008
-
-#define ET_TXMAC_FLOWCTRL		0x3010
-
-#define ET_RXMAC_CTRL			0x4000
-#define ET_RXMAC_CTRL_ENABLE		0x00000001
-#define ET_RXMAC_CTRL_NO_PKTFILT	0x00000004
-#define ET_RXMAC_CTRL_WOL_DISABLE	0x00000008
-
-#define ET_WOL_CRC			0x4004
-#define ET_WOL_SA_LO			0x4010
-#define ET_WOL_SA_HI			0x4014
-#define ET_WOL_MASK			0x4018
-
-#define ET_UCAST_FILTADDR1		0x4068
-#define ET_UCAST_FILTADDR2		0x406c
-#define ET_UCAST_FILTADDR3		0x4070
-
-#define ET_MULTI_HASH			0x4074
-
-#define ET_PKTFILT			0x4084
-#define ET_PKTFILT_BCAST		0x00000001
-#define ET_PKTFILT_MCAST		0x00000002
-#define ET_PKTFILT_UCAST		0x00000004
-#define ET_PKTFILT_FRAG			0x00000008
-#define ET_PKTFILT_MINLEN_MASK		0x007F0000
-#define ET_PKTFILT_MINLEN_SHIFT		16
-
-#define ET_RXMAC_MC_SEGSZ		0x4088
-#define ET_RXMAC_MC_SEGSZ_ENABLE	0x00000001
-#define ET_RXMAC_MC_SEGSZ_FC		0x00000002
-#define ET_RXMAC_MC_SEGSZ_MAX_MASK	0x000003FC
-#define ET_RXMAC_SEGSZ(segsz)		((segsz) / ET_MEM_UNIT)
-#define ET_RXMAC_CUT_THRU_FRMLEN	8074
-
-#define ET_RXMAC_MC_WATERMARK		0x408c
-#define ET_RXMAC_SPACE_AVL		0x4094
-
-#define ET_RXMAC_MGT			0x4098
-#define ET_RXMAC_MGT_PASS_ECRC		0x00000010
-#define ET_RXMAC_MGT_PASS_ELEN		0x00000020
-#define ET_RXMAC_MGT_PASS_ETRUNC	0x00010000
-#define ET_RXMAC_MGT_CHECK_PKT		0x00020000
-
-#define ET_MAC_CFG1			0x5000
-#define ET_MAC_CFG1_TXEN		0x00000001
-#define ET_MAC_CFG1_SYNC_TXEN		0x00000002
-#define ET_MAC_CFG1_RXEN		0x00000004
-#define ET_MAC_CFG1_SYNC_RXEN		0x00000008
-#define ET_MAC_CFG1_TXFLOW		0x00000010
-#define ET_MAC_CFG1_RXFLOW		0x00000020
-#define ET_MAC_CFG1_LOOPBACK		0x00000100
-#define ET_MAC_CFG1_RST_TXFUNC		0x00010000
-#define ET_MAC_CFG1_RST_RXFUNC		0x00020000
-#define ET_MAC_CFG1_RST_TXMC		0x00040000
-#define ET_MAC_CFG1_RST_RXMC		0x00080000
-#define ET_MAC_CFG1_SIM_RST		0x40000000
-#define ET_MAC_CFG1_SOFT_RST		0x80000000
-
-#define ET_MAC_CFG2			0x5004
-#define ET_MAC_CFG2_FDX			0x00000001
-#define ET_MAC_CFG2_CRC			0x00000002
-#define ET_MAC_CFG2_PADCRC		0x00000004
-#define ET_MAC_CFG2_LENCHK		0x00000010
-#define ET_MAC_CFG2_BIGFRM		0x00000020
-#define ET_MAC_CFG2_MODE_MII		0x00000100
-#define ET_MAC_CFG2_MODE_GMII		0x00000200
-#define ET_MAC_CFG2_PREAMBLE_LEN_MASK	0x0000F000
-#define ET_MAC_CFG2_PREAMBLE_LEN_SHIFT	12
-
-#define ET_IPG				0x5008
-#define ET_IPG_B2B_MASK			0x0000007F
-#define ET_IPG_MINIFG_MASK		0x0000FF00
-#define ET_IPG_NONB2B_2_MASK		0x007F0000
-#define ET_IPG_NONB2B_1_MASK		0x7F000000
-#define ET_IPG_B2B_SHIFT		0
-#define ET_IPG_MINIFG_SHIFT		8
-#define ET_IPG_NONB2B_2_SHIFT		16
-#define ET_IPG_NONB2B_1_SHIFT		24
-
-#define ET_MAC_HDX			0x500c
-#define ET_MAC_HDX_COLLWIN_MASK		0x000003FF
-#define ET_MAC_HDX_REXMIT_MAX_MASK	0x0000F000
-#define ET_MAC_HDX_EXC_DEFER		0x00010000
-#define ET_MAC_HDX_NOBACKOFF		0x00020000
-#define ET_MAC_HDX_BP_NOBACKOFF		0x00040000
-#define ET_MAC_HDX_ALT_BEB		0x00080000
-#define ET_MAC_HDX_ALT_BEB_TRUNC_MASK	0x00F00000
-#define ET_MAC_HDX_COLLWIN_SHIFT	0
-#define ET_MAC_HDX_REXMIT_MAX_SHIFT	12
-#define ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT	20
-
-#define ET_MAX_FRMLEN			0x5010
-
-#define ET_MII_CFG			0x5020
-#define ET_MII_CFG_CLKRST		0x00000007
-#define ET_MII_CFG_PREAMBLE_SUP		0x00000010
-#define ET_MII_CFG_SCAN_AUTOINC		0x00000020
-#define ET_MII_CFG_RST			0x80000000
-
-#define ET_MII_CMD			0x5024
-#define ET_MII_CMD_READ			0x00000001
-
-#define ET_MII_ADDR			0x5028
-#define ET_MII_ADDR_REG_MASK		0x0000001F
-#define ET_MII_ADDR_PHY_MASK		0x00001F00
-#define ET_MII_ADDR_REG_SHIFT		0
-#define ET_MII_ADDR_PHY_SHIFT		8
-
-#define ET_MII_CTRL			0x502c
-#define ET_MII_CTRL_VALUE_MASK		0x0000FFFF
-#define ET_MII_CTRL_VALUE_SHIFT		0
-
-#define ET_MII_STAT			0x5030
-#define ET_MII_STAT_VALUE_MASK		0x0000FFFF
-
-#define ET_MII_IND			0x5034
-#define ET_MII_IND_BUSY			0x00000001
-#define ET_MII_IND_INVALID		0x00000004
-
-#define ET_MAC_CTRL			0x5038
-#define ET_MAC_CTRL_MODE_MII		0x01000000
-#define ET_MAC_CTRL_LHDX		0x02000000
-#define ET_MAC_CTRL_GHDX		0x04000000
+#define	ET_TXQUEUE_START		0x0000
+#define	ET_TXQUEUE_END			0x0004
+#define	ET_RXQUEUE_START		0x0008
+#define	ET_RXQUEUE_END			0x000C
+#define	ET_QUEUE_ADDR(addr)		(((addr) / ET_MEM_UNIT) - 1)
+#define	ET_QUEUE_ADDR_START		0
+#define	ET_QUEUE_ADDR_END		ET_QUEUE_ADDR(ET_MEM_SIZE)
+
+#define	ET_PM				0x0010
+#define	EM_PM_GIGEPHY_ENB		0x00000001
+#define	ET_PM_SYSCLK_GATE		0x00000008
+#define	ET_PM_TXCLK_GATE		0x00000010
+#define	ET_PM_RXCLK_GATE		0x00000020
+#define	ET_PM_PHY_SW_COMA		0x00000040
+
+#define	ET_INTR_STATUS			0x0018
+#define	ET_INTR_MASK			0x001C
+
+#define	ET_SWRST			0x0028
+#define	ET_SWRST_TXDMA			0x00000001
+#define	ET_SWRST_RXDMA			0x00000002
+#define	ET_SWRST_TXMAC			0x00000004
+#define	ET_SWRST_RXMAC			0x00000008
+#define	ET_SWRST_MAC			0x00000010
+#define	ET_SWRST_MAC_STAT		0x00000020
+#define	ET_SWRST_MMC			0x00000040
+#define	ET_SWRST_SELFCLR_DISABLE	0x80000000
+
+#define	ET_MSI_CFG			0x0030
+
+#define	ET_LOOPBACK			0x0034
+
+#define	ET_TIMER			0x0038
+
+#define	ET_TXDMA_CTRL			0x1000
+#define	ET_TXDMA_CTRL_HALT		0x00000001
+#define	ET_TXDMA_CTRL_CACHE_THR_MASK	0x000000F0
+#define	ET_TXDMA_CTRL_SINGLE_EPKT	0x00000100	/* ??? */
+
+#define	ET_TX_RING_HI			0x1004
+#define	ET_TX_RING_LO			0x1008
+#define	ET_TX_RING_CNT			0x100C
+
+#define	ET_TX_STATUS_HI			0x101C
+#define	ET_TX_STATUS_LO			0x1020
+
+#define	ET_TX_READY_POS			0x1024
+#define	ET_TX_READY_POS_INDEX_MASK	0x000003FF
+#define	ET_TX_READY_POS_WRAP		0x00000400
+
+#define	ET_TX_DONE_POS			0x1060
+#define	ET_TX_DONE_POS_INDEX_MASK	0x0000003FF
+#define	ET_TX_DONE_POS_WRAP		0x000000400
+
+#define	ET_RXDMA_CTRL			0x2000
+#define	ET_RXDMA_CTRL_HALT		0x00000001
+#define	ET_RXDMA_CTRL_RING0_SIZE_MASK	0x00000300
+#define	ET_RXDMA_CTRL_RING0_128		0x00000000	/* 127 */
+#define	ET_RXDMA_CTRL_RING0_256		0x00000100	/* 255 */
+#define	ET_RXDMA_CTRL_RING0_512		0x00000200	/* 511 */
+#define	ET_RXDMA_CTRL_RING0_1024	0x00000300	/* 1023 */
+#define	ET_RXDMA_CTRL_RING0_ENABLE	0x00000400
+#define	ET_RXDMA_CTRL_RING1_SIZE_MASK	0x00001800
+#define	ET_RXDMA_CTRL_RING1_2048	0x00000000	/* 2047 */
+#define	ET_RXDMA_CTRL_RING1_4096	0x00000800	/* 4095 */
+#define	ET_RXDMA_CTRL_RING1_8192	0x00001000	/* 8191 */
+#define	ET_RXDMA_CTRL_RING1_16384	0x00001800	/* 16383 (9022?) */
+#define	ET_RXDMA_CTRL_RING1_ENABLE	0x00002000
+#define	ET_RXDMA_CTRL_HALTED		0x00020000
+
+#define	ET_RX_STATUS_LO			0x2004
+#define	ET_RX_STATUS_HI			0x2008
+
+#define	ET_RX_INTR_NPKTS		0x200C
+#define	ET_RX_INTR_DELAY		0x2010
+
+#define	ET_RXSTAT_LO			0x2020
+#define	ET_RXSTAT_HI			0x2024
+#define	ET_RXSTAT_CNT			0x2028
+
+#define	ET_RXSTAT_POS			0x2030
+#define	ET_RXSTAT_POS_INDEX_MASK	0x00000FFF
+#define	ET_RXSTAT_POS_WRAP		0x00001000
+
+#define	ET_RXSTAT_MINCNT		0x2038
+
+#define	ET_RX_RING0_LO			0x203C
+#define	ET_RX_RING0_HI			0x2040
+#define	ET_RX_RING0_CNT			0x2044
+
+#define	ET_RX_RING0_POS			0x204C
+#define	ET_RX_RING0_POS_INDEX_MASK	0x000003FF
+#define	ET_RX_RING0_POS_WRAP		0x00000400
+
+#define	ET_RX_RING0_MINCNT		0x2054
+
+#define	ET_RX_RING1_LO			0x2058
+#define	ET_RX_RING1_HI			0x205C
+#define	ET_RX_RING1_CNT			0x2060
+
+#define	ET_RX_RING1_POS			0x2068
+#define	ET_RX_RING1_POS_INDEX		0x000003FF
+#define	ET_RX_RING1_POS_WRAP		0x00000400
+
+#define	ET_RX_RING1_MINCNT		0x2070
+
+#define	ET_TXMAC_CTRL			0x3000
+#define	ET_TXMAC_CTRL_ENABLE		0x00000001
+#define	ET_TXMAC_CTRL_FC_DISABLE	0x00000008
+
+#define	ET_TXMAC_FLOWCTRL		0x3010
+#define	ET_TXMAC_FLOWCTRL_CFPT_MASK	0x0000FFFF
+#define	ET_TXMAC_FLOWCTRL_CFEP_MASK	0xFFFF0000
+#define	ET_TXMAC_FLOWCTRL_CFPT_SHIFT	0
+
+#define	ET_TXMAC_BP_CTRL		0x3020
+#define	ET_TXMAC_BP_CTRL_XONXOFF	0x00000001
+#define	ET_TXMAC_BP_CTRL_REQ		0x00000002
+
+#define	ET_RXMAC_CTRL			0x4000
+#define	ET_RXMAC_CTRL_ENABLE		0x00000001
+#define	ET_RXMAC_CTRL_NO_PKTFILT	0x00000004
+#define	ET_RXMAC_CTRL_WOL_DISABLE	0x00000008
+
+#define	ET_WOL_CRC			0x4004
+#define	ET_WOL_SA_LO			0x4010
+#define	ET_WOL_SA_HI			0x4014
+#define	ET_WOL_MASK			0x4018
+
+#define	ET_UCAST_FILTADDR1		0x4068
+#define	ET_UCAST_FILTADDR2		0x406C
+#define	ET_UCAST_FILTADDR3		0x4070
+
+#define	ET_MULTI_HASH			0x4074
+
+#define	ET_PKTFILT			0x4084
+#define	ET_PKTFILT_BCAST		0x00000001
+#define	ET_PKTFILT_MCAST		0x00000002
+#define	ET_PKTFILT_UCAST		0x00000004
+#define	ET_PKTFILT_FRAG			0x00000008
+#define	ET_PKTFILT_MINLEN_MASK		0x007F0000
+#define	ET_PKTFILT_MINLEN_SHIFT		16
+
+#define	ET_RXMAC_MC_SEGSZ		0x4088
+#define	ET_RXMAC_MC_SEGSZ_ENABLE	0x00000001
+#define	ET_RXMAC_MC_SEGSZ_FC		0x00000002
+#define	ET_RXMAC_MC_SEGSZ_MAX_MASK	0x000003FC
+#define	ET_RXMAC_SEGSZ(segsz)		((segsz) / ET_MEM_UNIT)
+#define	ET_RXMAC_CUT_THRU_FRMLEN	8074
+
+#define	ET_RXMAC_MC_WATERMARK		0x408C
+#define	ET_RXMAC_SPACE_AVL		0x4094
+
+#define	ET_RXMAC_MGT			0x4098
+#define	ET_RXMAC_MGT_PASS_ECRC		0x00000010
+#define	ET_RXMAC_MGT_PASS_ELEN		0x00000020
+#define	ET_RXMAC_MGT_PASS_ETRUNC	0x00010000
+#define	ET_RXMAC_MGT_CHECK_PKT		0x00020000
+
+#define	ET_MAC_CFG1			0x5000
+#define	ET_MAC_CFG1_TXEN		0x00000001
+#define	ET_MAC_CFG1_SYNC_TXEN		0x00000002
+#define	ET_MAC_CFG1_RXEN		0x00000004
+#define	ET_MAC_CFG1_SYNC_RXEN		0x00000008
+#define	ET_MAC_CFG1_TXFLOW		0x00000010
+#define	ET_MAC_CFG1_RXFLOW		0x00000020
+#define	ET_MAC_CFG1_LOOPBACK		0x00000100
+#define	ET_MAC_CFG1_RST_TXFUNC		0x00010000
+#define	ET_MAC_CFG1_RST_RXFUNC		0x00020000
+#define	ET_MAC_CFG1_RST_TXMC		0x00040000
+#define	ET_MAC_CFG1_RST_RXMC		0x00080000
+#define	ET_MAC_CFG1_SIM_RST		0x40000000
+#define	ET_MAC_CFG1_SOFT_RST		0x80000000
+
+#define	ET_MAC_CFG2			0x5004
+#define	ET_MAC_CFG2_FDX			0x00000001
+#define	ET_MAC_CFG2_CRC			0x00000002
+#define	ET_MAC_CFG2_PADCRC		0x00000004
+#define	ET_MAC_CFG2_LENCHK		0x00000010
+#define	ET_MAC_CFG2_BIGFRM		0x00000020
+#define	ET_MAC_CFG2_MODE_MII		0x00000100
+#define	ET_MAC_CFG2_MODE_GMII		0x00000200
+#define	ET_MAC_CFG2_PREAMBLE_LEN_MASK	0x0000F000
+#define	ET_MAC_CFG2_PREAMBLE_LEN_SHIFT	12
+
+#define	ET_IPG				0x5008
+#define	ET_IPG_B2B_MASK			0x0000007F
+#define	ET_IPG_MINIFG_MASK		0x0000FF00
+#define	ET_IPG_NONB2B_2_MASK		0x007F0000
+#define	ET_IPG_NONB2B_1_MASK		0x7F000000
+#define	ET_IPG_B2B_SHIFT		0
+#define	ET_IPG_MINIFG_SHIFT		8
+#define	ET_IPG_NONB2B_2_SHIFT		16
+#define	ET_IPG_NONB2B_1_SHIFT		24
+
+#define	ET_MAC_HDX			0x500C
+#define	ET_MAC_HDX_COLLWIN_MASK		0x000003FF
+#define	ET_MAC_HDX_REXMIT_MAX_MASK	0x0000F000
+#define	ET_MAC_HDX_EXC_DEFER		0x00010000
+#define	ET_MAC_HDX_NOBACKOFF		0x00020000
+#define	ET_MAC_HDX_BP_NOBACKOFF		0x00040000
+#define	ET_MAC_HDX_ALT_BEB		0x00080000
+#define	ET_MAC_HDX_ALT_BEB_TRUNC_MASK	0x00F00000
+#define	ET_MAC_HDX_COLLWIN_SHIFT	0
+#define	ET_MAC_HDX_REXMIT_MAX_SHIFT	12
+#define	ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT	20
+
+#define	ET_MAX_FRMLEN			0x5010
+
+#define	ET_MII_CFG			0x5020
+#define	ET_MII_CFG_CLKRST		0x00000007
+#define	ET_MII_CFG_PREAMBLE_SUP		0x00000010
+#define	ET_MII_CFG_SCAN_AUTOINC		0x00000020
+#define	ET_MII_CFG_RST			0x80000000
+
+#define	ET_MII_CMD			0x5024
+#define	ET_MII_CMD_READ			0x00000001
+
+#define	ET_MII_ADDR			0x5028
+#define	ET_MII_ADDR_REG_MASK		0x0000001F
+#define	ET_MII_ADDR_PHY_MASK		0x00001F00
+#define	ET_MII_ADDR_REG_SHIFT		0
+#define	ET_MII_ADDR_PHY_SHIFT		8
+
+#define	ET_MII_CTRL			0x502C
+#define	ET_MII_CTRL_VALUE_MASK		0x0000FFFF
+#define	ET_MII_CTRL_VALUE_SHIFT		0
+
+#define	ET_MII_STAT			0x5030
+#define	ET_MII_STAT_VALUE_MASK		0x0000FFFF
+
+#define	ET_MII_IND			0x5034
+#define	ET_MII_IND_BUSY			0x00000001
+#define	ET_MII_IND_INVALID		0x00000004
+
+#define	ET_MAC_CTRL			0x5038
+#define	ET_MAC_CTRL_MODE_MII		0x01000000
+#define	ET_MAC_CTRL_LHDX		0x02000000
+#define	ET_MAC_CTRL_GHDX		0x04000000
 
-#define ET_MAC_ADDR1			0x5040
-#define ET_MAC_ADDR2			0x5044
+#define	ET_MAC_ADDR1			0x5040
+#define	ET_MAC_ADDR2			0x5044
 
 /* MAC statistics counters. */
 #define	ET_STAT_PKTS_64			0x6080
@@ -364,48 +371,48 @@
 #define	ET_STAT_TX_UNDERSIZE		0x6128
 #define	ET_STAT_TX_FRAG			0x612C
 
-#define ET_MMC_CTRL			0x7000
-#define ET_MMC_CTRL_ENABLE		0x00000001
-#define ET_MMC_CTRL_ARB_DISABLE		0x00000002
-#define ET_MMC_CTRL_RXMAC_DISABLE	0x00000004
-#define ET_MMC_CTRL_TXMAC_DISABLE	0x00000008
-#define ET_MMC_CTRL_TXDMA_DISABLE	0x00000010
-#define ET_MMC_CTRL_RXDMA_DISABLE	0x00000020
-#define ET_MMC_CTRL_FORCE_CE		0x00000040
+#define	ET_MMC_CTRL			0x7000
+#define	ET_MMC_CTRL_ENABLE		0x00000001
+#define	ET_MMC_CTRL_ARB_DISABLE		0x00000002
+#define	ET_MMC_CTRL_RXMAC_DISABLE	0x00000004
+#define	ET_MMC_CTRL_TXMAC_DISABLE	0x00000008
+#define	ET_MMC_CTRL_TXDMA_DISABLE	0x00000010
+#define	ET_MMC_CTRL_RXDMA_DISABLE	0x00000020
+#define	ET_MMC_CTRL_FORCE_CE		0x00000040
 
 /*
  * Interrupts
  */
-#define ET_INTR_TXEOF			0x00000008
-#define ET_INTR_TXDMA_ERROR		0x00000010
-#define ET_INTR_RXEOF			0x00000020
-#define ET_INTR_RXRING0_LOW		0x00000040
-#define ET_INTR_RXRING1_LOW		0x00000080
-#define ET_INTR_RXSTAT_LOW		0x00000100
-#define ET_INTR_RXDMA_ERROR		0x00000200
-#define ET_INTR_TIMER			0x00004000
-#define ET_INTR_WOL			0x00008000
-#define ET_INTR_PHY			0x00010000
-#define ET_INTR_TXMAC			0x00020000
-#define ET_INTR_RXMAC			0x00040000
-#define ET_INTR_MAC_STATS		0x00080000
-#define ET_INTR_SLAVE_TO		0x00100000
-
-#define ET_INTRS			(ET_INTR_TXEOF | \
-					 ET_INTR_RXEOF | \
-					 ET_INTR_TIMER)
+#define	ET_INTR_TXDMA			0x00000008
+#define	ET_INTR_TXDMA_ERROR		0x00000010
+#define	ET_INTR_RXDMA			0x00000020
+#define	ET_INTR_RXRING0_LOW		0x00000040
+#define	ET_INTR_RXRING1_LOW		0x00000080
+#define	ET_INTR_RXSTAT_LOW		0x00000100
+#define	ET_INTR_RXDMA_ERROR		0x00000200
+#define	ET_INTR_TIMER			0x00004000
+#define	ET_INTR_WOL			0x00008000
+#define	ET_INTR_PHY			0x00010000
+#define	ET_INTR_TXMAC			0x00020000
+#define	ET_INTR_RXMAC			0x00040000
+#define	ET_INTR_MAC_STATS		0x00080000
+#define	ET_INTR_SLAVE_TO		0x00100000
+
+#define	ET_INTRS						\
+	(ET_INTR_TXDMA | ET_INTR_RXDMA | ET_INTR_TIMER |	\
+	 ET_INTR_TXDMA_ERROR | ET_INTR_RXDMA_ERROR)
 
 /*
  * RX ring position uses same layout
  */
-#define ET_RX_RING_POS_INDEX_MASK	0x000003FF
-#define ET_RX_RING_POS_WRAP		0x00000400
+#define	ET_RX_RING_POS_INDEX_MASK	0x000003FF
+#define	ET_RX_RING_POS_WRAP		0x00000400
 
 /*
  * PCI IDs
  */
-#define PCI_VENDOR_LUCENT		0x11c1
-#define PCI_PRODUCT_LUCENT_ET1310	0xed00		/* ET1310 10/100/1000M Ethernet */
-#define PCI_PRODUCT_LUCENT_ET1310_FAST	0xed01		/* ET1310 10/100M Ethernet */
+#define	PCI_VENDOR_LUCENT		0x11C1
+#define	PCI_PRODUCT_LUCENT_ET1310	0xED00		/* ET1310 10/100/1000M Ethernet */
+#define	PCI_PRODUCT_LUCENT_ET1310_FAST	0xED01		/* ET1310 10/100M Ethernet */
 
 #endif	/* !_IF_ETREG_H */

Modified: stable/9/sys/dev/et/if_etvar.h
==============================================================================
--- stable/9/sys/dev/et/if_etvar.h	Fri Jan  6 21:28:29 2012	(r229735)
+++ stable/9/sys/dev/et/if_etvar.h	Fri Jan  6 21:43:26 2012	(r229736)
@@ -38,39 +38,39 @@
 #ifndef _IF_ETVAR_H
 #define _IF_ETVAR_H
 
-#define ET_RING_ALIGN		4096
-#define ET_STATUS_ALIGN		8
-#define ET_NSEG_MAX		32	/* XXX no limit actually */
-#define ET_NSEG_SPARE		4
-
-#define ET_TX_NDESC		512
-#define ET_RX_NDESC		512
-#define ET_RX_NRING		2
-#define ET_RX_NSTAT		(ET_RX_NRING * ET_RX_NDESC)
-
-#define ET_TX_RING_SIZE		(ET_TX_NDESC * sizeof(struct et_txdesc))
-#define ET_RX_RING_SIZE		(ET_RX_NDESC * sizeof(struct et_rxdesc))
-#define ET_RXSTAT_RING_SIZE	(ET_RX_NSTAT * sizeof(struct et_rxstat))
+#define	ET_RING_ALIGN		4096
+#define	ET_STATUS_ALIGN		8
+#define	ET_NSEG_MAX		32	/* XXX no limit actually */
+#define	ET_NSEG_SPARE		4
+
+#define	ET_TX_NDESC		512
+#define	ET_RX_NDESC		512
+#define	ET_RX_NRING		2
+#define	ET_RX_NSTAT		(ET_RX_NRING * ET_RX_NDESC)
+
+#define	ET_TX_RING_SIZE		(ET_TX_NDESC * sizeof(struct et_txdesc))
+#define	ET_RX_RING_SIZE		(ET_RX_NDESC * sizeof(struct et_rxdesc))
+#define	ET_RXSTAT_RING_SIZE	(ET_RX_NSTAT * sizeof(struct et_rxstat))
 
-#define ET_JUMBO_FRAMELEN	(ET_MEM_SIZE - ET_MEM_RXSIZE_MIN -	\
+#define	ET_JUMBO_FRAMELEN	(ET_MEM_SIZE - ET_MEM_RXSIZE_MIN -	\
 				 ET_MEM_TXSIZE_EX)
-#define ET_JUMBO_MTU		(ET_JUMBO_FRAMELEN - ETHER_HDR_LEN -	\
+#define	ET_JUMBO_MTU		(ET_JUMBO_FRAMELEN - ETHER_HDR_LEN -	\
 				 EVL_ENCAPLEN - ETHER_CRC_LEN)
 
-#define ET_FRAMELEN(mtu)	(ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +	\
+#define	ET_FRAMELEN(mtu)	(ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +	\
 				 (mtu) + ETHER_CRC_LEN)
 
-#define ET_JSLOTS		(ET_RX_NDESC + 128)
-#define ET_JLEN			(ET_JUMBO_FRAMELEN + ETHER_ALIGN)
-#define ET_JUMBO_MEM_SIZE	(ET_JSLOTS * ET_JLEN)
+#define	ET_JSLOTS		(ET_RX_NDESC + 128)
+#define	ET_JLEN			(ET_JUMBO_FRAMELEN + ETHER_ALIGN)
+#define	ET_JUMBO_MEM_SIZE	(ET_JSLOTS * ET_JLEN)
 
-#define CSR_WRITE_4(sc, reg, val)	\
+#define	CSR_WRITE_4(sc, reg, val)	\
 	bus_write_4((sc)->sc_mem_res, (reg), (val))
-#define CSR_READ_4(sc, reg)		\
+#define	CSR_READ_4(sc, reg)		\
 	bus_read_4((sc)->sc_mem_res, (reg))
 
-#define ET_ADDR_HI(addr)	((uint64_t) (addr) >> 32)
-#define ET_ADDR_LO(addr)	((uint64_t) (addr) & 0xffffffff)
+#define	ET_ADDR_HI(addr)	((uint64_t) (addr) >> 32)
+#define	ET_ADDR_LO(addr)	((uint64_t) (addr) & 0xffffffff)
 
 struct et_txdesc {
 	uint32_t	td_addr_hi;
@@ -79,23 +79,23 @@ struct et_txdesc {
 	uint32_t	td_ctrl2;	/* ET_TDCTRL2_ */
 };
 
-#define ET_TDCTRL1_LEN_MASK	0x0000FFFF
+#define	ET_TDCTRL1_LEN_MASK	0x0000FFFF
 
-#define ET_TDCTRL2_LAST_FRAG	0x00000001
-#define ET_TDCTRL2_FIRST_FRAG	0x00000002
-#define ET_TDCTRL2_INTR		0x00000004
-#define ET_TDCTRL2_CTRL_WORD	0x00000008
-#define ET_TDCTRL2_HDX_BACKP	0x00000010
-#define ET_TDCTRL2_XMIT_PAUSE	0x00000020
-#define ET_TDCTRL2_FRAME_ERR	0x00000040
-#define ET_TDCTRL2_NO_CRC	0x00000080
-#define ET_TDCTRL2_MAC_OVRRD	0x00000100
-#define ET_TDCTRL2_PAD_PACKET	0x00000200
-#define ET_TDCTRL2_JUMBO_PACKET	0x00000400
-#define ET_TDCTRL2_INS_VLAN	0x00000800
-#define ET_TDCTRL2_CSUM_IP	0x00001000
-#define ET_TDCTRL2_CSUM_TCP	0x00002000
-#define ET_TDCTRL2_CSUM_UDP	0x00004000
+#define	ET_TDCTRL2_LAST_FRAG	0x00000001
+#define	ET_TDCTRL2_FIRST_FRAG	0x00000002
+#define	ET_TDCTRL2_INTR		0x00000004
+#define	ET_TDCTRL2_CTRL_WORD	0x00000008
+#define	ET_TDCTRL2_HDX_BACKP	0x00000010
+#define	ET_TDCTRL2_XMIT_PAUSE	0x00000020
+#define	ET_TDCTRL2_FRAME_ERR	0x00000040
+#define	ET_TDCTRL2_NO_CRC	0x00000080
+#define	ET_TDCTRL2_MAC_OVRRD	0x00000100
+#define	ET_TDCTRL2_PAD_PACKET	0x00000200
+#define	ET_TDCTRL2_JUMBO_PACKET	0x00000400
+#define	ET_TDCTRL2_INS_VLAN	0x00000800
+#define	ET_TDCTRL2_CSUM_IP	0x00001000
+#define	ET_TDCTRL2_CSUM_TCP	0x00002000
+#define	ET_TDCTRL2_CSUM_UDP	0x00004000
 
 struct et_rxdesc {
 	uint32_t	rd_addr_lo;
@@ -103,56 +103,56 @@ struct et_rxdesc {
 	uint32_t	rd_ctrl;	/* ET_RDCTRL_ */
 };
 
-#define ET_RDCTRL_BUFIDX_MASK	0x000003FF
+#define	ET_RDCTRL_BUFIDX_MASK	0x000003FF
 
 struct et_rxstat {
 	uint32_t	rxst_info1;
 	uint32_t	rxst_info2;	/* ET_RXST_INFO2_ */
 };
 
-#define ET_RXST_INFO1_HASH_PASS		0x00000001
-#define ET_RXST_INFO1_IPCSUM		0x00000002
-#define ET_RXST_INFO1_IPCSUM_OK		0x00000004
-#define ET_RXST_INFO1_TCPCSUM		0x00000008
-#define ET_RXST_INFO1_TCPCSUM_OK	0x00000010
-#define ET_RXST_INFO1_WOL		0x00000020
-#define ET_RXST_INFO1_RXMAC_ERR		0x00000040
-#define ET_RXST_INFO1_DROP		0x00000080
-#define ET_RXST_INFO1_FRAME_TRUNC	0x00000100
-#define ET_RXST_INFO1_JUMBO		0x00000200
-#define ET_RXST_INFO1_VLAN		0x00000400
-#define ET_RXST_INFO1_PREV_FRMAE_DROP	0x00010000
-#define ET_RXST_INFO1_SHORT		0x00020000
-#define ET_RXST_INFO1_BAD_CARRIER	0x00040000
-#define ET_RXST_INFO1_CODE_ERR		0x00080000
-#define ET_RXST_INFO1_CRC_ERR		0x00100000
-#define ET_RXST_INFO1_LEN_MISMATCH	0x00200000
-#define ET_RXST_INFO1_TOO_LONG		0x00400000
-#define ET_RXST_INFO1_OK		0x00800000
-#define ET_RXST_INFO1_MULTICAST		0x01000000
-#define ET_RXST_INFO1_BROADCAST		0x02000000
-#define ET_RXST_INFO1_DRIBBLE		0x04000000
-#define ET_RXST_INFO1_CTL_FRAME		0x08000000
-#define ET_RXST_INFO1_PAUSE_FRAME	0x10000000
-#define ET_RXST_INFO1_UNKWN_CTL_FRAME	0x20000000

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***



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