From owner-p4-projects@FreeBSD.ORG Wed Nov 12 06:34:28 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 53B5410656A6; Wed, 12 Nov 2008 06:34:28 +0000 (UTC) Delivered-To: perforce@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id F34D5106568E for ; Wed, 12 Nov 2008 06:34:27 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id E6CC88FC1A for ; Wed, 12 Nov 2008 06:34:27 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id mAC6YRCM051790 for ; Wed, 12 Nov 2008 06:34:27 GMT (envelope-from gonzo@FreeBSD.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id mAC6YRRr051788 for perforce@freebsd.org; Wed, 12 Nov 2008 06:34:27 GMT (envelope-from gonzo@FreeBSD.org) Date: Wed, 12 Nov 2008 06:34:27 GMT Message-Id: <200811120634.mAC6YRRr051788@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to gonzo@FreeBSD.org using -f From: Oleksandr Tymoshenko To: Perforce Change Reviews Cc: Subject: PERFORCE change 152853 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 12 Nov 2008 06:34:28 -0000 http://perforce.freebsd.org/chv.cgi?CH=152853 Change 152853 by gonzo@gonzo_jeeves on 2008/11/12 06:34:25 - Add definitions related to CommonChip core and PCI core Affected files ... .. //depot/projects/mips2/src/sys/dev/siba/sibareg.h#4 edit Differences ... ==== //depot/projects/mips2/src/sys/dev/siba/sibareg.h#4 (text+ko) ==== @@ -30,42 +30,95 @@ */ #ifndef _SIBA_SIBAREG_H_ -#define _SIBA_SIBAREG_H_ +#define _SIBA_SIBAREG_H_ -#define SIBA_CORE_LEN 0x00001000 /* Size of cfg per core */ -#define SIBA_CFG_END 0x00010000 /* Upper bound of cfg space */ -#define SIBA_MAX_CORES (SIBA_CFG_END/SIBA_CORE_LEN) /* #max cores */ +#define SIBA_CORE_LEN 0x00001000 /* Size of cfg per core */ +#define SIBA_CFG_END 0x00010000 /* Upper bound of cfg space */ +#define SIBA_MAX_CORES (SIBA_CFG_END/SIBA_CORE_LEN) /* #max cores */ /* offset of high ID register */ -#define SIBA_CORE_IDLO 0x00000ff8 -#define SIBA_CORE_IDHI 0x00000ffc +#define SIBA_CORE_IDLO 0x00000ff8 +#define SIBA_CORE_IDHI 0x00000ffc /* * Offsets of ChipCommon core registers. - * XXX: move to siba_cc */ -#define SIBA_CC_UART0 0x00000300 /* offset of UART0 */ -#define SIBA_CC_UART1 0x00000400 /* offset of UART1 */ +#define SIBA_CC_UART0 0x00000300 /* offset of UART0 */ +#define SIBA_CC_UART1 0x00000400 /* offset of UART1 */ + +#define SIBA_CC_CCID 0x0000 +#define SIBA_CC_IDMASK 0x0000FFFF +#define SIBA_CC_REVMASK 0x000F0000 +#define SIBA_CC_REVSHIFT 16 +#define SIBA_CC_PACKMASK 0x00F00000 +#define SIBA_CC_PACKSHIFT 20 +#define SIBA_CC_NRCORESMASK 0x0F000000 +#define SIBA_CC_NRCORESSHIFT 24 + +#define SIBA_IDHIGH_RCLO 0x0000000F /* Revision Code (low part) */ +#define SIBA_IDHIGH_CC 0x00008FF0 /* Core Code */ +#define SIBA_IDHIGH_CC_SHIFT 4 +#define SIBA_IDHIGH_RCHI 0x00007000 /* Revision Code (high part) */ +#define SIBA_IDHIGH_RCHI_SHIFT 8 +#define SIBA_IDHIGH_VC 0xFFFF0000 /* Vendor Code */ +#define SIBA_IDHIGH_VC_SHIFT 16 + +#define SIBA_CC_CAPABILITIES 0x0004 +#define SIBA_CC_CAP_UARTN_MASK 0x00000003 +#define SIBA_CC_CAP_MIPS_BE_MASK 0x00000004 +#define SIBA_CC_CAP_EXT_BUS_MASK 0x000000C0 +#define SIBA_CC_CAP_FLASH_MASK 0x00000700 +#define SIBA_CC_CAP_FLASH_SHIFT 16 +#define SIBA_CC_CAP_JTAG_MASK 0x00400000 +#define SIBA_CC_CAP_64_BPLANE 0x08000000 +#define SIBA_CC_CORECONTROL 0x0008 +/* OTP registers */ +#define SIBA_CC_OTP_STATUS 0x0010 +#define SIBA_CC_OTP_CONTROL 0x0014 +#define SIBA_CC_OTP_PROG 0x0018 +/* Interrupt registers */ +#define SIBA_CC_INTR_STATUS 0x0020 +#define SIBA_CC_INTR_MASK 0x0024 +#define SIBA_CC_CHIP_CONTROL 0x0028 +#define SIBA_CC_CHIP_STATUS 0x002C +/* JTAG registers */ +#define SIBA_JTAG_CMD 0x0030 +#define SIBA_JTAG_IR 0x0034 +#define SIBA_JTAG_DR 0x0038 +#define SIBA_JTAG_CTL 0x003C + +#define SIBA_CCID_BCM4710 0x4710 +#define SIBA_CCID_BCM4704 0x4704 +#define SIBA_CCID_SENTRY5 0x5365 + +/* PCI core registers */ +#define SIBA_PCI_CTL 0x0000 +#define SIBA_PCI_CTL_RST_EN 0x0001 +#define SIBA_PCI_CTL_RST 0x0002 +#define SIBA_PCI_CTL_CLK_EN 0x0004 +#define SIBA_PCI_CTL_CLK 0x0008 +#define SIBA_PCI_ARBITER_CTL 0x0010 +#define SIBA_PCI_ARBITER_INT 0x01 +#define SIBA_PCI_ARBITER_EXT 0x02 + +#define SIBA_PCI_BP_INTR_STATUS 0x0020 +#define SIBA_PCI_BP_INTR_MASK 0x0024 +#define SIBA_PCI_BP_PCI_MBOX 0x0028 -#define SIBA_CC_CCID 0x0000 -#define SIBA_CC_IDMASK 0x0000FFFF -#define SIBA_CC_REVMASK 0x000F0000 -#define SIBA_CC_REVSHIFT 16 -#define SIBA_CC_PACKMASK 0x00F00000 -#define SIBA_CC_PACKSHIFT 20 -#define SIBA_CC_NRCORESMASK 0x0F000000 -#define SIBA_CC_NRCORESSHIFT 24 +#define SIBA_PCI_BP_BCAST_ADDR 0x0050 +#define SIBA_PCI_BP_BCAST_DATA 0x0054 -#define SIBA_IDHIGH_RCLO 0x0000000F /* Revision Code (low part) */ -#define SIBA_IDHIGH_CC 0x00008FF0 /* Core Code */ -#define SIBA_IDHIGH_CC_SHIFT 4 -#define SIBA_IDHIGH_RCHI 0x00007000 /* Revision Code (high part) */ -#define SIBA_IDHIGH_RCHI_SHIFT 8 -#define SIBA_IDHIGH_VC 0xFFFF0000 /* Vendor Code */ -#define SIBA_IDHIGH_VC_SHIFT 16 +#define SIBA_PCI_GPIO_IN 0x0060 +#define SIBA_PCI_GPIO_OUT 0x0064 +#define SIBA_PCI_GPIO_ENABLE 0x0068 +#define SIBA_PCI_GPIO_CTL 0x006C -#define SIBA_CCID_BCM4710 0x4710 -#define SIBA_CCID_BCM4704 0x4704 -#define SIBA_CCID_SENTRY5 0x5365 +#define SIBA_PCI_TRANS0 0x0100 +#define SIBA_PCI_TRANS_MEM 0x00 +#define SIBA_PCI_TRANS_IO 0x01 +#define SIBA_PCI_TRANS_CFG0 0x02 +#define SIBA_PCI_TRANS_CFG1 0x03 +#define SIBA_PCI_TRANS1 0x0104 +#define SIBA_PCI_TRANS2 0x0108 #endif /* _SIBA_SIBAREG_H_ */