From owner-svn-src-projects@FreeBSD.ORG Sun Feb 22 16:28:25 2015 Return-Path: Delivered-To: svn-src-projects@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 682D9F62; Sun, 22 Feb 2015 16:28:25 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 51582663; Sun, 22 Feb 2015 16:28:25 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t1MGSP5W024728; Sun, 22 Feb 2015 16:28:25 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t1MGSPxw024726; Sun, 22 Feb 2015 16:28:25 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201502221628.t1MGSPxw024726@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sun, 22 Feb 2015 16:28:25 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r279166 - projects/clang360-import/contrib/llvm/patches X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 22 Feb 2015 16:28:25 -0000 Author: dim Date: Sun Feb 22 16:28:24 2015 New Revision: 279166 URL: https://svnweb.freebsd.org/changeset/base/279166 Log: Belatedly add llvm patch corresponding to r278367. Added: projects/clang360-import/contrib/llvm/patches/patch-08-llvm-r227089-fix-mips-i128.diff projects/clang360-import/contrib/llvm/patches/patch-09-llvm-r230058-indirectbrs-assert.diff - copied, changed from r279163, projects/clang360-import/contrib/llvm/patches/patch-08-llvm-r230058-indirectbrs-assert.diff Deleted: projects/clang360-import/contrib/llvm/patches/patch-08-llvm-r230058-indirectbrs-assert.diff Added: projects/clang360-import/contrib/llvm/patches/patch-08-llvm-r227089-fix-mips-i128.diff ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/clang360-import/contrib/llvm/patches/patch-08-llvm-r227089-fix-mips-i128.diff Sun Feb 22 16:28:24 2015 (r279166) @@ -0,0 +1,1950 @@ +Pull in r227087 from upstream llvm trunk (by Vasileios Kalintiris): + + [mips] Add tests for bitwise binary and integer arithmetic operators. + + Reviewers: dsanders + + Subscribers: llvm-commits + + Differential Revision: http://reviews.llvm.org/D7125 + +Pull in r227089 from upstream llvm trunk (by Vasileios Kalintiris): + + [mips] Enable arithmetic and binary operations for the i128 data type. + + Summary: + This patch adds support for some operations that were missing from + 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these + changes we can support the __int128_t and __uint128_t data types + from C/C++. + + Depends on D7125 + + Reviewers: dsanders + + Subscribers: llvm-commits + + Differential Revision: http://reviews.llvm.org/D7143 + +This fixes "error in backend" messages, when compiling parts of +compiler-rt using 128-bit integer types for mips64. + +Reported by: sbruno +PR: 197259 + +Introduced here: http://svnweb.freebsd.org/changeset/base/278367 + +Index: lib/Target/Mips/Mips64InstrInfo.td +=================================================================== +--- lib/Target/Mips/Mips64InstrInfo.td ++++ lib/Target/Mips/Mips64InstrInfo.td +@@ -440,6 +440,16 @@ def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)), + // bswap MipsPattern + def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>; + ++// Carry pattern ++def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs), ++ (DSUBu GPR64:$lhs, GPR64:$rhs)>; ++let AdditionalPredicates = [NotDSP] in { ++ def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs), ++ (DADDu GPR64:$lhs, GPR64:$rhs)>; ++ def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm), ++ (DADDiu GPR64:$lhs, imm:$imm)>; ++} ++ + //===----------------------------------------------------------------------===// + // Instruction aliases + //===----------------------------------------------------------------------===// +Index: lib/Target/Mips/MipsISelLowering.cpp +=================================================================== +--- lib/Target/Mips/MipsISelLowering.cpp ++++ lib/Target/Mips/MipsISelLowering.cpp +@@ -261,6 +261,9 @@ MipsTargetLowering::MipsTargetLowering(const MipsT + setOperationAction(ISD::LOAD, MVT::i64, Custom); + setOperationAction(ISD::STORE, MVT::i64, Custom); + setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); ++ setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); ++ setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); ++ setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); + } + + if (!Subtarget.isGP64bit()) { +@@ -2017,10 +2020,11 @@ SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDVa + SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, + SelectionDAG &DAG) const { + SDLoc DL(Op); ++ MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; ++ + SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); + SDValue Shamt = Op.getOperand(2); +- +- // if shamt < 32: ++ // if shamt < (VT.bits): + // lo = (shl lo, shamt) + // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) + // else: +@@ -2028,18 +2032,17 @@ SDValue MipsTargetLowering::lowerShiftLeftParts(SD + // hi = (shl lo, shamt[4:0]) + SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, + DAG.getConstant(-1, MVT::i32)); +- SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, +- DAG.getConstant(1, MVT::i32)); +- SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, +- Not); +- SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); +- SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); +- SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); ++ SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, ++ DAG.getConstant(1, VT)); ++ SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); ++ SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); ++ SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); ++ SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); + SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, + DAG.getConstant(0x20, MVT::i32)); +- Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, +- DAG.getConstant(0, MVT::i32), ShiftLeftLo); +- Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or); ++ Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ++ DAG.getConstant(0, VT), ShiftLeftLo); ++ Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); + + SDValue Ops[2] = {Lo, Hi}; + return DAG.getMergeValues(Ops, DL); +@@ -2050,8 +2053,9 @@ SDValue MipsTargetLowering::lowerShiftRightParts(S + SDLoc DL(Op); + SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); + SDValue Shamt = Op.getOperand(2); ++ MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; + +- // if shamt < 32: ++ // if shamt < (VT.bits): + // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) + // if isSRA: + // hi = (sra hi, shamt) +@@ -2066,21 +2070,19 @@ SDValue MipsTargetLowering::lowerShiftRightParts(S + // hi = 0 + SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, + DAG.getConstant(-1, MVT::i32)); +- SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, +- DAG.getConstant(1, MVT::i32)); +- SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not); +- SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); +- SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); +- SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, +- Hi, Shamt); ++ SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, ++ DAG.getConstant(1, VT)); ++ SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); ++ SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); ++ SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); ++ SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, ++ DL, VT, Hi, Shamt); + SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, + DAG.getConstant(0x20, MVT::i32)); +- SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi, +- DAG.getConstant(31, MVT::i32)); +- Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or); +- Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, +- IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32), +- ShiftRightHi); ++ SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, VT)); ++ Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); ++ Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ++ IsSRA ? Shift31 : DAG.getConstant(0, VT), ShiftRightHi); + + SDValue Ops[2] = {Lo, Hi}; + return DAG.getMergeValues(Ops, DL); +Index: lib/Target/Mips/MipsSEISelDAGToDAG.cpp +=================================================================== +--- lib/Target/Mips/MipsSEISelDAGToDAG.cpp ++++ lib/Target/Mips/MipsSEISelDAGToDAG.cpp +@@ -236,13 +236,31 @@ SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigne + (Opc == ISD::SUBC || Opc == ISD::SUBE)) && + "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn"); + ++ unsigned SLTuOp = Mips::SLTu, ADDuOp = Mips::ADDu; ++ if (Subtarget->isGP64bit()) { ++ SLTuOp = Mips::SLTu64; ++ ADDuOp = Mips::DADDu; ++ } ++ + SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) }; + SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1); + EVT VT = LHS.getValueType(); + +- SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops); +- SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT, ++ SDNode *Carry = CurDAG->getMachineNode(SLTuOp, DL, VT, Ops); ++ ++ if (Subtarget->isGP64bit()) { ++ // On 64-bit targets, sltu produces an i64 but our backend currently says ++ // that SLTu64 produces an i32. We need to fix this in the long run but for ++ // now, just make the DAG type-correct by asserting the upper bits are zero. ++ Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT, ++ CurDAG->getTargetConstant(0, VT), ++ SDValue(Carry, 0), ++ CurDAG->getTargetConstant(Mips::sub_32, VT)); ++ } ++ ++ SDNode *AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT, + SDValue(Carry, 0), RHS); ++ + return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, + SDValue(AddCarry, 0)); + } +@@ -641,7 +659,8 @@ std::pair MipsSEDAGToDAGISel::selec + + case ISD::SUBE: { + SDValue InFlag = Node->getOperand(2); +- Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node); ++ unsigned Opc = Subtarget->isGP64bit() ? Mips::DSUBu : Mips::SUBu; ++ Result = selectAddESubE(Opc, InFlag, InFlag.getOperand(0), DL, Node); + return std::make_pair(true, Result); + } + +@@ -649,7 +668,8 @@ std::pair MipsSEDAGToDAGISel::selec + if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC. + break; + SDValue InFlag = Node->getOperand(2); +- Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node); ++ unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu; ++ Result = selectAddESubE(Opc, InFlag, InFlag.getValue(0), DL, Node); + return std::make_pair(true, Result); + } + +Index: lib/Target/Mips/MipsSEISelLowering.cpp +=================================================================== +--- lib/Target/Mips/MipsSEISelLowering.cpp ++++ lib/Target/Mips/MipsSEISelLowering.cpp +@@ -122,6 +122,8 @@ MipsSETargetLowering::MipsSETargetLowering(const M + setOperationAction(ISD::MUL, MVT::i64, Custom); + + if (Subtarget.isGP64bit()) { ++ setOperationAction(ISD::SMUL_LOHI, MVT::i64, Custom); ++ setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom); + setOperationAction(ISD::MULHS, MVT::i64, Custom); + setOperationAction(ISD::MULHU, MVT::i64, Custom); + setOperationAction(ISD::SDIVREM, MVT::i64, Custom); +@@ -200,6 +202,8 @@ MipsSETargetLowering::MipsSETargetLowering(const M + if (Subtarget.hasMips64r6()) { + // MIPS64r6 replaces the accumulator-based multiplies with a three register + // instruction ++ setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); ++ setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); + setOperationAction(ISD::MUL, MVT::i64, Legal); + setOperationAction(ISD::MULHS, MVT::i64, Legal); + setOperationAction(ISD::MULHU, MVT::i64, Legal); +Index: test/CodeGen/Mips/llvm-ir/add.ll +=================================================================== +--- test/CodeGen/Mips/llvm-ir/add.ll ++++ test/CodeGen/Mips/llvm-ir/add.ll +@@ -0,0 +1,115 @@ ++; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 ++; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 ++; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 ++; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 ++; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 ++; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 ++; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 ++; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 ++; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 ++ ++define signext i1 @add_i1(i1 signext %a, i1 signext %b) { ++entry: ++; ALL-LABEL: add_i1: ++ ++ ; ALL: addu $[[T0:[0-9]+]], $4, $5 ++ ; ALL: sll $[[T0]], $[[T0]], 31 ++ ; ALL: sra $2, $[[T0]], 31 ++ ++ %r = add i1 %a, %b ++ ret i1 %r ++} ++ ++define signext i8 @add_i8(i8 signext %a, i8 signext %b) { ++entry: ++; ALL-LABEL: add_i8: ++ ++ ; NOT-R2-R6: addu $[[T0:[0-9]+]], $4, $5 ++ ; NOT-R2-R6: sll $[[T0]], $[[T0]], 24 ++ ; NOT-R2-R6: sra $2, $[[T0]], 24 ++ ++ ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 ++ ; R2-R6: seb $2, $[[T0:[0-9]+]] ++ ++ %r = add i8 %a, %b ++ ret i8 %r ++} ++ ++define signext i16 @add_i16(i16 signext %a, i16 signext %b) { ++entry: ++; ALL-LABEL: add_i16: ++ ++ ; NOT-R2-R6: addu $[[T0:[0-9]+]], $4, $5 ++ ; NOT-R2-R6: sll $[[T0]], $[[T0]], 16 ++ ; NOT-R2-R6: sra $2, $[[T0]], 16 ++ ++ ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 ++ ; R2-R6: seh $2, $[[T0:[0-9]+]] ++ ++ %r = add i16 %a, %b ++ ret i16 %r ++} ++ ++define signext i32 @add_i32(i32 signext %a, i32 signext %b) { ++entry: ++; ALL-LABEL: add_i32: ++ ++ ; ALL: addu $2, $4, $5 ++ ++ %r = add i32 %a, %b ++ ret i32 %r ++} ++ ++define signext i64 @add_i64(i64 signext %a, i64 signext %b) { ++entry: ++; ALL-LABEL: add_i64: ++ ++ ; GP32: addu $3, $5, $7 ++ ; GP32: sltu $[[T0:[0-9]+]], $3, $7 ++ ; GP32: addu $[[T1:[0-9]+]], $[[T0]], $6 ++ ; GP32: addu $2, $4, $[[T1]] ++ ++ ; GP64: daddu $2, $4, $5 ++ ++ %r = add i64 %a, %b ++ ret i64 %r ++} ++ ++define signext i128 @add_i128(i128 signext %a, i128 signext %b) { ++entry: ++; ALL-LABEL: add_i128: ++ ++ ; GP32: lw $[[T0:[0-9]+]], 28($sp) ++ ; GP32: addu $[[T1:[0-9]+]], $7, $[[T0]] ++ ; GP32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]] ++ ; GP32: lw $[[T3:[0-9]+]], 24($sp) ++ ; GP32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]] ++ ; GP32: addu $[[T5:[0-9]+]], $6, $[[T4]] ++ ; GP32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]] ++ ; GP32: lw $[[T7:[0-9]+]], 20($sp) ++ ; GP32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]] ++ ; GP32: lw $[[T9:[0-9]+]], 16($sp) ++ ; GP32: addu $3, $5, $[[T8]] ++ ; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]] ++ ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T9]] ++ ; GP32: addu $2, $4, $[[T11]] ++ ; GP32: move $4, $[[T5]] ++ ; GP32: move $5, $[[T1]] ++ ++ ; GP64: daddu $3, $5, $7 ++ ; GP64: sltu $[[T0:[0-9]+]], $3, $7 ++ ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6 ++ ; GP64: daddu $2, $4, $[[T1]] ++ ++ %r = add i128 %a, %b ++ ret i128 %r ++} +Index: test/CodeGen/Mips/llvm-ir/and.ll +=================================================================== +--- test/CodeGen/Mips/llvm-ir/and.ll ++++ test/CodeGen/Mips/llvm-ir/and.ll +@@ -0,0 +1,94 @@ ++; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP32 ++; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP32 ++; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP32 ++; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP32 ++; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 ++; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 ++; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 ++; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 ++; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 ++ ++define signext i1 @and_i1(i1 signext %a, i1 signext %b) { ++entry: ++; ALL-LABEL: and_i1: ++ ++ ; ALL: and $2, $4, $5 ++ ++ %r = and i1 %a, %b ++ ret i1 %r ++} ++ ++define signext i8 @and_i8(i8 signext %a, i8 signext %b) { ++entry: ++; ALL-LABEL: and_i8: ++ ++ ; ALL: and $2, $4, $5 ++ ++ %r = and i8 %a, %b ++ ret i8 %r ++} ++ ++define signext i16 @and_i16(i16 signext %a, i16 signext %b) { ++entry: ++; ALL-LABEL: and_i16: ++ ++ ; ALL: and $2, $4, $5 ++ ++ %r = and i16 %a, %b ++ ret i16 %r ++} ++ ++define signext i32 @and_i32(i32 signext %a, i32 signext %b) { ++entry: ++; ALL-LABEL: and_i32: ++ ++ ; GP32: and $2, $4, $5 ++ ++ ; GP64: and $[[T0:[0-9]+]], $4, $5 ++ ; GP64: sll $2, $[[T0]], 0 ++ ++ %r = and i32 %a, %b ++ ret i32 %r ++} ++ ++define signext i64 @and_i64(i64 signext %a, i64 signext %b) { ++entry: ++; ALL-LABEL: and_i64: ++ ++ ; GP32: and $2, $4, $6 ++ ; GP32: and $3, $5, $7 ++ ++ ; GP64: and $2, $4, $5 ++ ++ %r = and i64 %a, %b ++ ret i64 %r ++} ++ ++define signext i128 @and_i128(i128 signext %a, i128 signext %b) { ++entry: ++; ALL-LABEL: and_i128: ++ ++ ; GP32: lw $[[T0:[0-9]+]], 24($sp) ++ ; GP32: lw $[[T1:[0-9]+]], 20($sp) ++ ; GP32: lw $[[T2:[0-9]+]], 16($sp) ++ ; GP32: and $2, $4, $[[T2]] ++ ; GP32: and $3, $5, $[[T1]] ++ ; GP32: and $4, $6, $[[T0]] ++ ; GP32: lw $[[T3:[0-9]+]], 28($sp) ++ ; GP32: and $5, $7, $[[T3]] ++ ++ ; GP64: and $2, $4, $6 ++ ; GP64: and $3, $5, $7 ++ ++ %r = and i128 %a, %b ++ ret i128 %r ++} +Index: test/CodeGen/Mips/llvm-ir/ashr.ll +=================================================================== +--- test/CodeGen/Mips/llvm-ir/ashr.ll ++++ test/CodeGen/Mips/llvm-ir/ashr.ll +@@ -0,0 +1,188 @@ ++; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP32 \ ++; RUN: -check-prefix=M2 -check-prefix=NOT-R2-R6 ++; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \ ++; RUN: -check-prefix=32R1-R2 ++; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP32 \ ++; RUN: -check-prefix=32R1-R2 -check-prefix=R2-R6 ++; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP32 \ ++; RUN: -check-prefix=32R6 -check-prefix=R2-R6 ++; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 \ ++; RUN: -check-prefix=M3 -check-prefix=NOT-R2-R6 ++; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 \ ++; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 ++; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 \ ++; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 ++; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 \ ++; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6 ++; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 \ ++; RUN: -check-prefix=64R6 -check-prefix=R2-R6 ++ ++define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) { ++entry: ++; ALL-LABEL: ashr_i1: ++ ++ ; ALL: move $2, $4 ++ ++ %r = ashr i1 %a, %b ++ ret i1 %r ++} ++ ++define signext i8 @ashr_i8(i8 signext %a, i8 signext %b) { ++entry: ++; ALL-LABEL: ashr_i8: ++ ++ ; FIXME: The andi instruction is redundant. ++ ; ALL: andi $[[T0:[0-9]+]], $5, 255 ++ ; ALL: srav $2, $4, $[[T0]] ++ ++ %r = ashr i8 %a, %b ++ ret i8 %r ++} ++ ++define signext i16 @ashr_i16(i16 signext %a, i16 signext %b) { ++entry: ++; ALL-LABEL: ashr_i16: ++ ++ ; FIXME: The andi instruction is redundant. ++ ; ALL: andi $[[T0:[0-9]+]], $5, 65535 ++ ; ALL: srav $2, $4, $[[T0]] ++ ++ %r = ashr i16 %a, %b ++ ret i16 %r ++} ++ ++define signext i32 @ashr_i32(i32 signext %a, i32 signext %b) { ++entry: ++; ALL-LABEL: ashr_i32: ++ ++ ; ALL: srav $2, $4, $5 ++ ++ %r = ashr i32 %a, %b ++ ret i32 %r ++} ++ ++define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) { ++entry: ++; ALL-LABEL: ashr_i64: ++ ++ ; M2: srav $[[T0:[0-9]+]], $4, $7 ++ ; M2: andi $[[T1:[0-9]+]], $7, 32 ++ ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] ++ ; M2: move $3, $[[T0]] ++ ; M2: srlv $[[T2:[0-9]+]], $5, $7 ++ ; M2: not $[[T3:[0-9]+]], $7 ++ ; M2: sll $[[T4:[0-9]+]], $4, 1 ++ ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]] ++ ; M2: or $3, $[[T3]], $[[T2]] ++ ; M2: $[[BB0]]: ++ ; M2: beqz $[[T1]], $[[BB1:BB[0-9_]+]] ++ ; M2: nop ++ ; M2: sra $2, $4, 31 ++ ; M2: $[[BB1]]: ++ ; M2: jr $ra ++ ; M2: nop ++ ++ ; 32R1-R2: srlv $[[T0:[0-9]+]], $5, $7 ++ ; 32R1-R2: not $[[T1:[0-9]+]], $7 ++ ; 32R1-R2: sll $[[T2:[0-9]+]], $4, 1 ++ ; 32R1-R2: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] ++ ; 32R1-R2: or $3, $[[T3]], $[[T0]] ++ ; 32R1-R2: srav $[[T4:[0-9]+]], $4, $7 ++ ; 32R1-R2: andi $[[T5:[0-9]+]], $7, 32 ++ ; 32R1-R2: movn $3, $[[T4]], $[[T5]] ++ ; 32R1-R2: sra $4, $4, 31 ++ ; 32R1-R2: jr $ra ++ ; 32R1-R2: movn $2, $4, $[[T5]] ++ ++ ; 32R6: srav $[[T0:[0-9]+]], $4, $7 ++ ; 32R6: andi $[[T1:[0-9]+]], $7, 32 ++ ; 32R6: seleqz $[[T2:[0-9]+]], $[[T0]], $[[T1]] ++ ; 32R6: sra $[[T3:[0-9]+]], $4, 31 ++ ; 32R6: selnez $[[T4:[0-9]+]], $[[T3]], $[[T1]] ++ ; 32R6: or $[[T5:[0-9]+]], $[[T4]], $[[T2]] ++ ; 32R6: srlv $[[T6:[0-9]+]], $5, $7 ++ ; 32R6: not $[[T7:[0-9]+]], $7 ++ ; 32R6: sll $[[T8:[0-9]+]], $4, 1 ++ ; 32R6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]] ++ ; 32R6: or $[[T10:[0-9]+]], $[[T9]], $[[T6]] ++ ; 32R6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]] ++ ; 32R6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]] ++ ; 32R6: jr $ra ++ ; 32R6: or $3, $[[T0]], $[[T11]] ++ ++ ; FIXME: The sll instruction below is redundant. ++ ; GP64: sll $[[T0:[0-9]+]], $5, 0 ++ ; GP64: dsrav $2, $4, $[[T0]] ++ ++ %r = ashr i64 %a, %b ++ ret i64 %r ++} ++ ++define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) { ++entry: ++; ALL-LABEL: ashr_i128: ++ ++ ; GP32: lw $25, %call16(__ashrti3)($gp) ++ ++ ; M3: sll $[[T0:[0-9]+]], $7, 0 ++ ; M3: dsrav $[[T1:[0-9]+]], $4, $[[T0]] ++ ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32 ++ ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] ++ ; M3: move $3, $[[T1]] ++ ; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]] ++ ; M3: dsll $[[T5:[0-9]+]], $4, 1 ++ ; M3: not $[[T6:[0-9]+]], $[[T0]] ++ ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] ++ ; M3: or $3, $[[T7]], $[[T4]] ++ ; M3: $[[BB0]]: ++ ; M3: beqz $[[T3]], $[[BB1:BB[0-9_]+]] ++ ; M3: nop ++ ; M3: dsra $2, $4, 31 ++ ; M3: $[[BB1]]: ++ ; M3: jr $ra ++ ; M3: nop ++ ++ ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0 ++ ; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]] ++ ; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1 ++ ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]] ++ ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]] ++ ; GP64-NOT-R6: or $3, $[[T4]], $[[T1]] ++ ; GP64-NOT-R6: dsrav $2, $4, $[[T0]] ++ ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32 ++ ++ ; GP64-NOT-R6: movn $3, $2, $[[T5]] ++ ; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 31 ++ ; GP64-NOT-R6: jr $ra ++ ; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]] ++ ++ ; 64R6: sll $[[T0:[0-9]+]], $7, 0 ++ ; 64R6: dsrav $[[T1:[0-9]+]], $4, $[[T0]] ++ ; 64R6: andi $[[T2:[0-9]+]], $[[T0]], 32 ++ ; 64R6: sll $[[T3:[0-9]+]], $[[T2]], 0 ++ ; 64R6: seleqz $[[T4:[0-9]+]], $[[T1]], $[[T3]] ++ ; 64R6: dsra $[[T5:[0-9]+]], $4, 31 ++ ; 64R6: selnez $[[T6:[0-9]+]], $[[T5]], $[[T3]] ++ ; 64R6: or $2, $[[T6]], $[[T4]] ++ ; 64R6: dsrlv $[[T7:[0-9]+]], $5, $[[T0]] ++ ; 64R6: dsll $[[T8:[0-9]+]], $4, 1 ++ ; 64R6: not $[[T9:[0-9]+]], $[[T0]] ++ ; 64R6: dsllv $[[T10:[0-9]+]], $[[T8]], $[[T9]] ++ ; 64R6: or $[[T11:[0-9]+]], $[[T10]], $[[T7]] ++ ; 64R6: seleqz $[[T12:[0-9]+]], $[[T11]], $[[T3]] ++ ; 64R6: selnez $[[T13:[0-9]+]], $[[T1]], $[[T3]] ++ ; 64R6: jr $ra ++ ; 64R6: or $3, $[[T13]], $[[T12]] ++ ++ %r = ashr i128 %a, %b ++ ret i128 %r ++} +Index: test/CodeGen/Mips/llvm-ir/lshr.ll +=================================================================== +--- test/CodeGen/Mips/llvm-ir/lshr.ll ++++ test/CodeGen/Mips/llvm-ir/lshr.ll +@@ -0,0 +1,176 @@ ++; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP32 \ ++; RUN: -check-prefix=M2 -check-prefix=NOT-R2-R6 ++; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \ ++; RUN: -check-prefix=32R1-R2 ++; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP32 \ ++; RUN: -check-prefix=32R1-R2 -check-prefix=R2-R6 ++; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP32 \ ++; RUN: -check-prefix=32R6 -check-prefix=R2-R6 ++; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 \ ++; RUN: -check-prefix=M3 -check-prefix=NOT-R2-R6 ++; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 \ ++; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 ++; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 \ ++; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 ++; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 \ ++; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6 ++; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 \ ++; RUN: -check-prefix=64R6 -check-prefix=R2-R6 ++ ++define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) { ++entry: ++; ALL-LABEL: lshr_i1: ++ ++ ; ALL: move $2, $4 ++ ++ %r = lshr i1 %a, %b ++ ret i1 %r ++} ++ ++define zeroext i8 @lshr_i8(i8 zeroext %a, i8 zeroext %b) { ++entry: ++; ALL-LABEL: lshr_i8: ++ ++ ; ALL: srlv $[[T0:[0-9]+]], $4, $5 ++ ; ALL: andi $2, $[[T0]], 255 ++ ++ %r = lshr i8 %a, %b ++ ret i8 %r ++} ++ ++define zeroext i16 @lshr_i16(i16 zeroext %a, i16 zeroext %b) { ++entry: ++; ALL-LABEL: lshr_i16: ++ ++ ; ALL: srlv $[[T0:[0-9]+]], $4, $5 ++ ; ALL: andi $2, $[[T0]], 65535 ++ ++ %r = lshr i16 %a, %b ++ ret i16 %r ++} ++ ++define signext i32 @lshr_i32(i32 signext %a, i32 signext %b) { ++entry: ++; ALL-LABEL: lshr_i32: ++ ++ ; ALL: srlv $2, $4, $5 ++ ++ %r = lshr i32 %a, %b ++ ret i32 %r ++} ++ ++define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) { ++entry: ++; ALL-LABEL: lshr_i64: ++ ++ ; M2: srlv $[[T0:[0-9]+]], $4, $7 ++ ; M2: andi $[[T1:[0-9]+]], $7, 32 ++ ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] ++ ; M2: move $3, $[[T0]] ++ ; M2: srlv $[[T2:[0-9]+]], $5, $7 ++ ; M2: not $[[T3:[0-9]+]], $7 ++ ; M2: sll $[[T4:[0-9]+]], $4, 1 ++ ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]] ++ ; M2: or $3, $[[T3]], $[[T2]] ++ ; M2: $[[BB0]]: ++ ; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]] ++ ; M2: addiu $2, $zero, 0 ++ ; M2: move $2, $[[T0]] ++ ; M2: $[[BB1]]: ++ ; M2: jr $ra ++ ; M2: nop ++ ++ ; 32R1-R2: srlv $[[T0:[0-9]+]], $5, $7 ++ ; 32R1-R2: not $[[T1:[0-9]+]], $7 ++ ; 32R1-R2: sll $[[T2:[0-9]+]], $4, 1 ++ ; 32R1-R2: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] ++ ; 32R1-R2: or $3, $[[T3]], $[[T0]] ++ ; 32R1-R2: srlv $[[T4:[0-9]+]], $4, $7 ++ ; 32R1-R2: andi $[[T5:[0-9]+]], $7, 32 ++ ; 32R1-R2: movn $3, $[[T4]], $[[T5]] ++ ; 32R1-R2: jr $ra ++ ; 32R1-R2: movn $2, $zero, $[[T5]] ++ ++ ; 32R6: srlv $[[T0:[0-9]+]], $5, $7 ++ ; 32R6: not $[[T1:[0-9]+]], $7 ++ ; 32R6: sll $[[T2:[0-9]+]], $4, 1 ++ ; 32R6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] ++ ; 32R6: or $[[T4:[0-9]+]], $[[T3]], $[[T0]] ++ ; 32R6: andi $[[T5:[0-9]+]], $7, 32 ++ ; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T3]] ++ ; 32R6: srlv $[[T7:[0-9]+]], $4, $7 ++ ; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] ++ ; 32R6: or $3, $[[T8]], $[[T6]] ++ ; 32R6: jr $ra ++ ; 32R6: seleqz $2, $[[T7]], $[[T5]] ++ ++ ; GP64: sll $[[T0:[0-9]+]], $5, 0 ++ ; GP64: dsrlv $2, $4, $[[T0]] ++ ++ %r = lshr i64 %a, %b ++ ret i64 %r ++} ++ ++define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) { ++entry: ++; ALL-LABEL: lshr_i128: ++ ++ ; GP32: lw $25, %call16(__lshrti3)($gp) ++ ++ ; M3: sll $[[T0:[0-9]+]], $7, 0 ++ ; M3: dsrlv $[[T1:[0-9]+]], $4, $[[T0]] ++ ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32 ++ ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] ++ ; M3: move $3, $[[T1]] ++ ; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]] ++ ; M3: dsll $[[T5:[0-9]+]], $4, 1 ++ ; M3: not $[[T6:[0-9]+]], $[[T0]] ++ ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] ++ ; M3: or $3, $[[T7]], $[[T4]] ++ ; M3: $[[BB0]]: ++ ; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]] ++ ; M3: daddiu $2, $zero, 0 ++ ; M3: move $2, $[[T1]] ++ ; M3: $[[BB1]]: ++ ; M3: jr $ra ++ ; M3: nop ++ ++ ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0 ++ ; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]] ++ ; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1 ++ ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]] ++ ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]] ++ ; GP64-NOT-R6: or $3, $[[T4]], $[[T1]] ++ ; GP64-NOT-R6: dsrlv $2, $4, $[[T0]] ++ ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32 ++ ; GP64-NOT-R6: movn $3, $2, $[[T5]] ++ ; GP64-NOT-R6: jr $ra ++ ; GP64-NOT-R6: movn $2, $zero, $1 ++ ++ ; 64R6: sll $[[T0:[0-9]+]], $7, 0 ++ ; 64R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]] ++ ; 64R6: dsll $[[T2:[0-9]+]], $4, 1 ++ ; 64R6: not $[[T3:[0-9]+]], $[[T0]] ++ ; 64R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]] ++ ; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T1]] ++ ; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 32 ++ ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 ++ ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] ++ ; 64R6: dsrlv $[[T9:[0-9]+]], $4, $[[T0]] ++ ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] ++ ; 64R6: or $3, $[[T10]], $[[T8]] ++ ; 64R6: jr $ra ++ ; 64R6: seleqz $2, $[[T0]], $[[T7]] ++ ++ %r = lshr i128 %a, %b ++ ret i128 %r ++} +Index: test/CodeGen/Mips/llvm-ir/mul.ll +=================================================================== +--- test/CodeGen/Mips/llvm-ir/mul.ll ++++ test/CodeGen/Mips/llvm-ir/mul.ll +@@ -1,19 +1,19 @@ +-; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +-; RUN: -check-prefix=ALL -check-prefix=M2 +-; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +-; RUN: -check-prefix=ALL -check-prefix=32R1-R2 -check-prefix=32R1 +-; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +-; RUN: -check-prefix=ALL -check-prefix=32R1-R2 -check-prefix=32R2 +-; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +-; RUN: -check-prefix=ALL -check-prefix=32R6 +-; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +-; RUN: -check-prefix=ALL -check-prefix=M4 +-; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +-; RUN: -check-prefix=ALL -check-prefix=64R1-R2 +-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +-; RUN: -check-prefix=ALL -check-prefix=64R1-R2 +-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +-; RUN: -check-prefix=ALL -check-prefix=64R6 ++; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL \ ++; RUN: -check-prefix=M2 -check-prefix=GP32 ++; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL \ ++; RUN: -check-prefix=32R1-R2 -check-prefix=GP32 ++; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL \ ++; RUN: -check-prefix=32R1-R2 -check-prefix=32R2 -check-prefix=GP32 ++; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL \ ++; RUN: -check-prefix=32R6 -check-prefix=GP32 ++; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL \ ++; RUN: -check-prefix=M4 -check-prefix=GP64-NOT-R6 ++; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL \ ++; RUN: -check-prefix=64R1-R2 -check-prefix=GP64-NOT-R6 ++; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL \ ++; RUN: -check-prefix=64R1-R2 -check-prefix=GP64 -check-prefix=GP64-NOT-R6 ++; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL \ ++; RUN: -check-prefix=64R6 + + define signext i1 @mul_i1(i1 signext %a, i1 signext %b) { + entry: +@@ -179,3 +179,30 @@ entry: + %r = mul i64 %a, %b + ret i64 %r + } ++ ++define signext i128 @mul_i128(i128 signext %a, i128 signext %b) { ++entry: ++; ALL-LABEL: mul_i128: ++ ++ ; GP32: lw $25, %call16(__multi3)($gp) ++ ++ ; GP64-NOT-R6: dmult $4, $7 ++ ; GP64-NOT-R6: mflo $[[T0:[0-9]+]] ++ ; GP64-NOT-R6: dmult $5, $6 ++ ; GP64-NOT-R6: mflo $[[T1:[0-9]+]] ++ ; GP64-NOT-R6: dmultu $5, $7 ++ ; GP64-NOT-R6: mflo $3 ++ ; GP64-NOT-R6: mfhi $[[T2:[0-9]+]] ++ ; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] ++ ; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]] ++ ++ ; 64R6: dmul $[[T0:[0-9]+]], $5, $6 ++ ; 64R6: dmuhu $[[T1:[0-9]+]], $5, $7 ++ ; 64R6: daddu $[[T2:[0-9]+]], $[[T1]], $[[T0]] ++ ; 64R6: dmul $[[T3:[0-9]+]], $4, $7 ++ ; 64R6: daddu $2, $[[T2]], $[[T3]] ++ ; 64R6: dmul $3, $5, $7 ++ ++ %r = mul i128 %a, %b ++ ret i128 %r ++} +Index: test/CodeGen/Mips/llvm-ir/or.ll +=================================================================== +--- test/CodeGen/Mips/llvm-ir/or.ll ++++ test/CodeGen/Mips/llvm-ir/or.ll +@@ -0,0 +1,95 @@ ++; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP32 ++; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP32 ++; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP32 ++; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP32 ++; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 ++; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 ++; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 ++; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 ++; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ ++; RUN: -check-prefix=ALL -check-prefix=GP64 ++ ++define signext i1 @or_i1(i1 signext %a, i1 signext %b) { ++entry: ++; ALL-LABEL: or_i1: ++ ++ ; ALL: or $2, $4, $5 ++ ++ %r = or i1 %a, %b ++ ret i1 %r ++} ++ ++define signext i8 @or_i8(i8 signext %a, i8 signext %b) { ++entry: ++; ALL-LABEL: or_i8: ++ ++ ; ALL: or $2, $4, $5 ++ ++ %r = or i8 %a, %b ++ ret i8 %r ++} ++ ++define signext i16 @or_i16(i16 signext %a, i16 signext %b) { ++entry: ++; ALL-LABEL: or_i16: ++ ++ ; ALL: or $2, $4, $5 ++ ++ %r = or i16 %a, %b ++ ret i16 %r ++} ++ ++define signext i32 @or_i32(i32 signext %a, i32 signext %b) { ++entry: ++; ALL-LABEL: or_i32: ++ ++ ; GP32: or $2, $4, $5 ++ ++ ; GP64: or $[[T0:[0-9]+]], $4, $5 ++ ; FIXME: The sll instruction below is redundant. ++ ; GP64: sll $2, $[[T0]], 0 ++ ++ %r = or i32 %a, %b ++ ret i32 %r ++} ++ ++define signext i64 @or_i64(i64 signext %a, i64 signext %b) { ++entry: ++; ALL-LABEL: or_i64: ++ ++ ; GP32: or $2, $4, $6 ++ ; GP32: or $3, $5, $7 ++ ++ ; GP64: or $2, $4, $5 ++ ++ %r = or i64 %a, %b ++ ret i64 %r ++} ++ ++define signext i128 @or_i128(i128 signext %a, i128 signext %b) { ++entry: ++; ALL-LABEL: or_i128: ++ ++ ; GP32: lw $[[T0:[0-9]+]], 24($sp) ++ ; GP32: lw $[[T1:[0-9]+]], 20($sp) ++ ; GP32: lw $[[T2:[0-9]+]], 16($sp) ++ ; GP32: or $2, $4, $[[T2]] ++ ; GP32: or $3, $5, $[[T1]] ++ ; GP32: or $4, $6, $[[T0]] ++ ; GP32: lw $[[T3:[0-9]+]], 28($sp) ++ ; GP32: or $5, $7, $[[T3]] ++ ++ ; GP64: or $2, $4, $6 ++ ; GP64: or $3, $5, $7 *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***