From owner-p4-projects@FreeBSD.ORG Mon Jun 2 22:36:18 2003 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id EF3CC37B404; Mon, 2 Jun 2003 22:36:17 -0700 (PDT) Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id A593237B401 for ; Mon, 2 Jun 2003 22:36:17 -0700 (PDT) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id 0B8BF43FB1 for ; Mon, 2 Jun 2003 22:36:17 -0700 (PDT) (envelope-from jmallett@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.12.6/8.12.6) with ESMTP id h535aG0U040810 for ; Mon, 2 Jun 2003 22:36:16 -0700 (PDT) (envelope-from jmallett@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.12.6/8.12.6/Submit) id h535aG2i040807 for perforce@freebsd.org; Mon, 2 Jun 2003 22:36:16 -0700 (PDT) Date: Mon, 2 Jun 2003 22:36:16 -0700 (PDT) Message-Id: <200306030536.h535aG2i040807@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to jmallett@freebsd.org using -f From: Juli Mallett To: Perforce Change Reviews Subject: PERFORCE change 32456 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Jun 2003 05:36:19 -0000 http://perforce.freebsd.org/chv.cgi?CH=32456 Change 32456 by jmallett@jmallett_dalek on 2003/06/02 22:35:22 Update for C99 CPP. Affected files ... .. //depot/projects/mips/sys/mips/mips/locore.S#8 edit Differences ... ==== //depot/projects/mips/sys/mips/mips/locore.S#8 (text+ko) ==== @@ -28,7 +28,6 @@ #include #include -#incldue #include "assym.s" @@ -54,48 +53,54 @@ .globl btext btext: ENTRY(start) - # t0: Bits to preserve if set: - # Soft reset - # Boot exception vectors (firmware-provided) + /* + * t0: Bits to preserve if set: + * Soft reset + * Boot exception vectors (firmware-provided) + */ li t0, MIPS_SR_BEV | MIPS3_SR_SR - # t1: Bits to set explicitly: - # Kernel mode is 64-bit - # Enable FPU + /* + * t1: Bits to set explicitly: + * Kernel mode is 64-bit + * Enable FPU + */ li t1, MIPS3_SR_KX | MIPS_SR_COP_1_BIT - # Read coprocessor 0 status register, clear bits not - # preserved (namely, clearing interrupt bits), and set - # bits we want to explicitly set. + /* + * Read coprocessor 0 status register, clear bits not + * preserved (namely, clearing interrupt bits), and set + * bits we want to explicitly set. + */ mfc0 t2, MIPS_COP_0_STATUS and t2, t0 or t2, t1 mtc0 t2, MIPS_COP_0_STATUS COP0_SYNC - # Extra nops for the FPU to spin up. + /* Extra nops for the FPU to spin up. */ - # Clear cause register. + /* Clear cause register. */ mtc0 zero, MIPS_COP_0_CAUSE COP0_SYNC - # Read and store the PrID FPU ID for CPU identification. + /* Read and store the PrID FPU ID for CPU identification. */ mfc0 t0, MIPS_COP_0_PRID cfc1 t1, MIPS_FPU_ID sw t0, cpu_id sw t1, fpu_id - # Set up the GP. + /* Set up the GP. */ la gp, _gp - # Set up our temporary stack. + /* Set up our temporary stack. */ la sp, topstack - # Call the platform-specific startup code. + /* Call the platform-specific startup code. */ jal platform_start nop - # Start MI things rolling. + /* Start MI things rolling. */ jal mi_startup nop - # NOTREACHED + /* NOTREACHED */ END(start)